參數(shù)資料
型號(hào)： 7C1351-50
廠商： Cypress Semiconductor Corp.
英文描述： 128Kx36 Flow-Through SRAM with NoBL TM Architecture
中文描述： 128K × 36至流通過(guò)與總線延遲TM架構(gòu)的SRAM
文件頁(yè)數(shù)： 7/13頁(yè)
文件大?。?/td> 195K
代理商： 7C1351-50
CY7C1351
7
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
.....................................
65
°
C to
+
150
°
C
Ambient Temperature with
Power Applied
..................................................
55
°
C to
+
125
°
C
Supply Voltage on V
DD
Relative to GND
.........
0.5V to
+
4.6V
DC Voltage Applied to Outputs
in High Z State
[7]
.....................................
0.5V to V
DDQ
+
0.5V
DC Input Voltage
[7]
..................................
0.5V to V
DDQ
+
0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Operating Range
Range
Ambient
Temperature
[8]
V
DD
/V
DDQ
3.3V
±
5%
Com
’
l
0
°
C to
+
70
°
C
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
Min.
Max.
Unit
V
DD
Power Supply Voltage
3.135
3.465
V
V
DDQ
I/O Supply Voltage
3.135
3.465
V
V
OH
Output HIGH Voltage
V
DD
= Min., I
OH
=
–
4.0 mA
[9]
V
DD
= Min., I
OL
= 8.0 mA
[9]
2.4
V
V
OL
Output LOW Voltage
0.4
V
V
IH
Input HIGH Voltage
2.0
V
DD
+
0.3V
V
V
IL
Input LOW Voltage
[7]
–
0.3
0.8
V
I
X
Input Load Current
GND
≤
V
I
≤
V
DDQ
–
5
5
mA
Input Current of MODE
–
30
30
mA
I
OZ
Output Leakage
Current
GND
≤
V
I
≤
V
DDQ,
Output Disabled
–
5
5
mA
I
CC
V
DD
Operating Supply
V
DD
= Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
CYC
15-ns cycle, 66 MHz
250
mA
20-ns cycle, 50 MHz
200
mA
25-ns cycle, 40 MHz
175
mA
I
SB1
Automatic CE
Power-Down
Current
—
TTL Inputs
Max. V
DD
, Device Deselected,
V
IN
≥
V
IH
or V
IN
≤
V
IL
f = f
MAX
= 1/t
CYC
15-ns cycle, 66 MHz
60
mA
20-ns cycle, 50 MHz
40
mA
25-ns cycle, 40 MHz
35
mA
I
SB2
Automatic CE
Power-Down
Current
—
CMOS
Inputs
Max. V
DD
, Device Deselected,
V
IN
≤
0.3V or V
IN
> V
DDQ
–
0.3V,
f =0
All speed grades
5
mA
I
SB3
Automatic CE
Power-Down
Current
—
CMOS
Inputs
Max. V
DD
, Device Deselected, or
V
IN
≤
0.3V or V
IN
>
V
DDQ
–
0.3V
f = f
MAX
= 1/t
CYC
15-ns cycle, 66 MHz
50
mA
20-ns cycle, 50 MHz
40
mA
25-ns cycle, 40 MHz
35
mA
Notes:
7.
8.
9.
Minimum voltage equals
–
2.0V for pulse duration less than 20 ns.
T
is the case temperature.
The load used for V
OH
and V
OL
testing is shown in figure (b) of the AC Test Loads.
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