- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375093 > 7C1351-50 (Cypress Semiconductor Corp.) 128Kx36 Flow-Through SRAM with NoBL TM Architecture PDF資料下載
參數(shù)資料
| 型號(hào)： | 7C1351-50 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 128Kx36 Flow-Through SRAM with NoBL TM Architecture |
| 中文描述： | 128K × 36至流通過(guò)與總線延遲TM架構(gòu)的SRAM |
| 文件頁(yè)數(shù)： | 3/13頁(yè) |
| 文件大?。?/td> | 195K |
| 代理商： | 7C1351-50 |
第1頁(yè)第2頁(yè)當(dāng)前第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)
CY7C1351
3
Pin Definitions
Pin Number
50
–
44,
81
–
82, 99,
100, 32
–
37
96
–
93
Name
A
[16:0]
I/O
Input-
Synchronous
Description
Address Inputs used to select one of the 133,072 address locations. Sampled at
the rising edge of the CLK.
BWS
[3:0]
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the
SRAM. Sampled on the rising edge of CLK. BWS
0
controls DQ
[7:0]
and DP
0
, BWS
1
controls DQ
[15:8]
and DP
1
, BWS
2
controls DQ
[23:16]
and DP
2
, BWS
0
controls
DQ
[31:24]
and DP
3
.
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active
LOW. This signal must be asserted LOW to initiate a write sequence.
Advance/Load input used to advance the on-chip address counter or load a new
address. When HIGH (and CEN is asserted LOW) the internal burst counter is
advanced. When LOW, a new address can be loaded into the device for an access.
After being deselected, ADV/LD should be driven LOW in order to load a new
address.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified
with CEN. CLK is only recognized if CEN is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
2
and CE
3
to select/deselect the device.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and CE
3
to select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and
CE
2
to select/deselect the device.
Output Enable, active LOW. Combined with the synchronous logic block inside the
device to control the direction of the I/O pins. When LOW, the I/O pins are allowed
to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act
as input data pins. OE is masked during the data portion of a write sequence,
during the first clock when emerging from a deselected state and when the device
has been deselected.
Clock Enable Input, active LOW. When asserted LOW the clock signal is recog-
nized by the SRAM. When deasserted HIGH the clock signal is masked. Since
deasserting CEN does not deselect the device, CEN can be used to extend the
previous cycle when required.
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by A
[16:0]
during the previous clock rise of the
read cycle. The direction of the pins is controlled by OE and the internal control
logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH,
DQ
[31:0]
are placed in a three-state condition. The outputs are automatically
three-stated during the data portion of a write sequence, during the first clock when
emerging from a deselected state, and when the device is deselected, regardless
of the state of OE.
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to
DQ
[31:0]
. During write sequences, DP
0
is controlled by BWS
0
, DP
1
is controlled by
BWS
1
, DP
2
is controlled by BWS
2
, and DP
3
is controlled by BWS
3
.
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved
burst order. Pulled LOW selects the linear burst order. MODE should not change
states during operation. When left floating MODE will default HIGH, to an inter-
leaved burst order.
Power supply inputs to the core of the device. Should be connected to 3.3V power
supply.
Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.
88
WE
Input-
Synchronous
Input-
Synchronous
85
ADV/LD
89
CLK
Input-Clock
98
CE
1
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
97
CE
2
92
CE
3
86
OE
87
CEN
Input-
Synchronous
29
–
28,
25
–
22,
19
–
18,
13
–
12, 9
–
6,
3
–
2, 79
–
78,
75
–
72,
69
–
68,
63
–
62,
59
–
56, 53
–
52
1, 30, 51, 80
DQ
[31:0]
I/O-
Synchronous
DP
[3:0]
I/O-
Synchronous
31
MODE
Input
Strap pin
15, 16, 41, 65,
91
4, 11, 20, 27,
54, 61, 70, 77
5, 10, 14, 17,
21, 26, 40, 60,
64, 66
–
67,
55, 71, 76, 90
V
DD
Power Supply
V
DDQ
I/O Power
Supply
Ground
V
SS
Ground for the device. Should be connected to ground of the system.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 7C1351-66 | 128Kx36 Flow-Through SRAM with NoBL TM Architecture |
| 7C1359A-100 | 256K x 18 Synchronous-Pipelined Cache Tag RAM |
| 7C1359A-133 | 256K x 18 Synchronous-Pipelined Cache Tag RAM |
| 7C1359A-150 | 256K x 18 Synchronous-Pipelined Cache Tag RAM |
| 7C1359A-166 | 256K x 18 Synchronous-Pipelined Cache Tag RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 7C1351-66 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:128Kx36 Flow-Through SRAM with NoBL TM Architecture |
| 7C1351G-117AZC | 制造商:Cypress Semiconductor 功能描述: |
| 7C1351G-133AZC | 制造商:Cypress Semiconductor 功能描述: |
| 7C1351GC | 制造商:Cypress Semiconductor 功能描述: |
| 7C1351XC | 制造商:Cypress Semiconductor 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。