參數(shù)資料
型號： 7C1351-50
廠商： Cypress Semiconductor Corp.
英文描述： 128Kx36 Flow-Through SRAM with NoBL TM Architecture
中文描述： 128K × 36至流通過與總線延遲TM架構(gòu)的SRAM
文件頁數(shù)： 6/13頁
文件大?。?/td> 195K
代理商： 7C1351-50
CY7C1351
6
Interleaved Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Write Cycle Description
[1, 2]
Function
WE
BWS
3
BWS
2
BWS
1
BWS
0
Read
1
X
X
X
X
Write
No bytes written
0
1
1
1
1
Write Byte 0
(DQ
[7:0]
and
DP
0
)
0
1
1
1
0
Write Byte 1
–
(DQ
[15:8]
and
DP
1
)
0
1
1
0
1
Write Bytes 1, 0
0
1
1
0
0
Write Byte 2
(DQ
[23:16]
and
DP
2
)
0
1
0
1
1
Write Bytes 2, 0
0
1
0
1
0
Write Bytes 2, 1
0
1
0
0
1
Write Bytes 2, 1, 0
0
1
0
0
0
Write Byte 3
(DQ
[31:24]
and
DP
3
)
0
0
1
1
1
Write Bytes 3, 0
0
0
1
1
0
Write Bytes 3, 1
0
0
1
0
1
Write Bytes 3, 1, 0
0
0
1
0
0
Write Bytes 3, 2
0
0
0
1
1
Write Bytes 3, 2, 0
0
0
0
1
0
Write Bytes 3, 2, 1
0
0
0
0
1
Write All Bytes
0
0
0
0
0
相關(guān)PDF資料
PDF描述
7C1351-66 128Kx36 Flow-Through SRAM with NoBL TM Architecture
7C1359A-100 256K x 18 Synchronous-Pipelined Cache Tag RAM
7C1359A-133 256K x 18 Synchronous-Pipelined Cache Tag RAM
7C1359A-150 256K x 18 Synchronous-Pipelined Cache Tag RAM
7C1359A-166 256K x 18 Synchronous-Pipelined Cache Tag RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
7C1351-66 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:128Kx36 Flow-Through SRAM with NoBL TM Architecture
7C1351G-117AZC 制造商:Cypress Semiconductor 功能描述:
7C1351G-133AZC 制造商:Cypress Semiconductor 功能描述:
7C1351GC 制造商:Cypress Semiconductor 功能描述:
7C1351XC 制造商:Cypress Semiconductor 功能描述:
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