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參數(shù)資料
| 型號： | 74F50109 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Synchronizing dual J-K positive edge-triggered flip-flop with metastable immune characteristics |
| 中文描述： | 同步雙JK正沿觸發(fā)器與亞穩(wěn)態(tài)觸發(fā)器免疫特性 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大小： | 97K |
| 代理商： | 74F50109 |
Philips Semiconductors
Product specification
74F50109
Synchronizing dual J–K positive edge-triggered
flip-flop with metastable immune characteristics
September 14, 1990
7
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
amb
= +25
°
C
V
CC
= +5.0V
C
L
= 50pF,
R
L
= 500
MIN
TYP
T
amb
= 0
°
C to +70
°
C
V
CC
= +5.0V
±
10%
C
L
= 50pF,
R
L
= 500
MIN
SYMBOL
PARAMETER
TEST
UNIT
CONDITION
MAX
MAX
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
sk(o)
NOTES:
1. | t
PN
actual – t
PM
actual| for any output compared to any other output where N and M are either LH or HL.
2. Skew times are valid only under same test conditions (temperature, V
CC
, loading, etc.,).
Maximum clock frequency
Waveform 1
130
150
90
ns
Propagation delay
CPn to Qn or Qn
Waveform 1
2.0
2.0
3.8
3.8
6.0
6.0
2.0
2.0
6.5
6.5
ns
Propagation delay
SDn, RDn
to Qn or Qn
Output skew
1, 2
Waveform 2
3.5
3.5
5.5
5.5
8.0
8.0
3.0
3.0
8.5
8.5
ns
Waveform 4
1.5
1.5
ns
AC SETUP REQUIREMENTS
LIMITS
T
amb
= +25
°
C
V
CC
= +5.0V
C
L
= 50pF,
R
L
= 500
MIN
TYP
T
amb
= 0
°
C to +70
°
C
V
CC
= +5.0V
±
10%
C
L
= 50pF,
R
L
= 500
MIN
SYMBOL
PARAMETER
TEST
UNIT
CONDITION
MAX
MAX
t
su
(H)
t
su
(L)
Setup time, high or low
Jn, Kn to CPn
Waveform 1
1.5
1.5
2.0
2.0
ns
t
h
(H)
t
h
(L)
Hold time, high or low
Jn, Kn to CPn
Waveform 1
1.0
1.0
1.5
1.5
ns
t
w
(H)
t
w
(L)
t
w
(L)
CPn pulse width,
high or low
Waveform 1
3.0
4.0
3.5
5.0
ns
SDn or RDn pulse width, low
Waveform 2
3.5
4.0
ns
t
rec
Recovery time
SDn or RDn to CP
Waveform 3
3.0
3.5
ns
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