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參數(shù)資料
| 型號： | 74F50109 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Synchronizing dual J-K positive edge-triggered flip-flop with metastable immune characteristics |
| 中文描述： | 同步雙JK正沿觸發(fā)器與亞穩(wěn)態(tài)觸發(fā)器免疫特性 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大小： | 97K |
| 代理商： | 74F50109 |
Philips Semiconductors
Product specification
74F50109
Synchronizing dual J–K positive edge-triggered
flip-flop with metastable immune characteristics
September 14, 1990
3
LOGIC DIAGRAM
V
= Pin 16
GND = Pin 8
K
Q
Q
CP
4, 12
3, 13
6, 10
7, 9
SF00601
1, 15
5, 11
RD
SD
J
2, 14
DESCRIPTION
The 74F50109 is a dual positive edge-triggered JK-type flip-flop
featuring individual J, K, clock, set, and reset inputs; also true and
complementary outputs.
Set (SD) and reset (RD) are asynchronous active low inputs and
operate independently of the clock (CP) input.
The J and K are edge–triggered inputs which control the state
changes of the flip–flops as described in the function table.
The J and K inputs must be stable just one setup time prior to the
low–to–high transition of the clock for guaranteed propagation
delays. The JK design allows operation as a D flip–flop by tying J
and K inputs together.
The 74F50109 is designed so that the outputs can never display a
metastable state due to setup and hold time violations. If setup time
and hold time are violated the propagation delays may be extended
beyond the specifications but the outputs will not glitch or display a
metastable state. Typical metastability parameters for the 74F50109
are:
τ 135
ps and
τ
9.8 X 10
6
sec where
τ
represents a function
of the rate at which a latch in a metastable state resolves that
condition and T
0
represents a function of the measurement of the
propensity of a latch to enter a metastable state.
METASTABLE IMMUNE CHARACTERISTICS
Philips Semiconductors uses the term ’metastable immune’ to
describe characteristics of some of the products in its FAST family.
Specifically the 74F50XXX family presently consist of 4 products
which displays metastable immune characteristics. This term means
that the outputs will not glitch or display an output anomaly under
any circumstances including setup and hold time violations.
This claim is easily verified on the 74F5074. By running two
independent signal generators (see Fig. 1) at nearly the same
frequency (in this case 10MHz clock and 10.02 MHz data) the
device–under–test can be often be driven into a metastable state. If
the Q output is then used to trigger a digital scope set to infinite
persistence the Q output will build a waveform.0 An experiment was
run by continuously operating the devices in the region where
metastability will occur.
When the device–under–test is a 74F74 (which was not designed
with metastable immune characteristics) the waveform will appear
as in Fig. 2.
Fig. 2 shows clearly that the Q output can vary in time with respect
to the Q trigger point. This also implies that the Q or Q output
waveshapes may be distorted. This can be verified on an analog
scope with a charge plate CRT. Perhaps of even greater interest are
the dots running along the 3.5V volt line in the upper right hand
quadrant. These show that the Q output did not change state even
though the Q output glitched to at least 1.5 volts, the trigger point of
the scope.
When the device–under–test is a metastable immune part, such as
the 74F5074, the waveform will appear as in Fig. 3. The 74F5074 Q
output will appear as in Fig. 3. The 74F5074 Q output will not vary
with respect to the Q trigger point even when the a part is driven into
a metastable state. Any tendency towards internal metastability is
resolved by Philips Semiconductors patented circuitry. If a
metastable event occurs within the flop the only outward
manifestation of the event will be an increased clock–to–Q/Q
propagation delay. This propagation delay is, of course, a function of
the metastability characteristics of the part defined by
τ
and T
0.
The metastability characteristics of the 74F5074 and related part
types represent state–of–the–art TTL technology.
After determining the T
0
and t of the flop, calculating the mean time
between failures (MTBF) is simple. Suppose a designer wants to
use the 74F50729 for synchronizing asynchronous data that is
arriving at 10MHz (as measured by a frequency counter), has a
clock frequency of 50MHz, and has decided that he would like to
sample the output of the 74F50109 10 nanoseconds after the clock
edge. He simply plugs his number into the equation below:
MTBF = e
(t’/t)
/ T
o
f
C
f
I
In this formula, f
C
is the frequency of the clock, f
I
is the average
input event frequency, and t’ is the time after the clock pulse that the
output is sampled (t’ < h, h being the normal propagation delay). In
this situation the f
I
will be twice the data frequency of 20 MHz
because input events consist of both of low and high transitions.
Multiplying f
I
by f
C
gives an answer of 10
15
Hz
2
. From Fig. 4 it is
clear that the MTBF is greater than 10
10
seconds. Using the above
formula MTBF is 1.51 X 10
10
seconds or about 480 years.
D
Q
Q
CP
TRIGGER
DIGITAL
SCOPE
INPUT
SIGNAL GENERATOR
SF00586
SIGNAL GENERATOR
Figure 1. Test setup
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