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| 型號： | 73M1966B-DB |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 40/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DEMO 73M1966B 20-TSSOP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1 |
| 系列： | * |
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DS_1x66B_001
73M1866B/73M1966B Data Sheet
Rev. 1.6
45
8
PCM Highway Interface and Signal Processing
The PCM highway is the method by which the 73M1x66B exchanges PCM data with the host or other
PCM-enabled devices. The PCM data can be in either 8-bit compressed mode or in 16-bit linear mode.
Compression of the received signals from the PSTN line interface is selectable A-
law or μ-law, as
specified by ITU-T Recommendation G.711. The 73M1x66B is configurable with respect to tuning the
clock and time slot relationships. See Section 8.1 for details.
The PCM interface provided by the 73M1x66B consists of the following signals:
PCLK
The frequency at which bits are driven on the PCM highway. (Goes to the PCLKI pin.)
FS
PCM frame synchronization pulse.
DX
PCM data transmitted to the PCM highway.
DR
PCM data received from the PCM highway.
The basic timing relationship of PCM highway interface signals is shown in Figure 20.
FS
PCLK
DX
MSB
LSB
Figure 20: 8-bit Transmission Example
8.1
PCM Highway Interface Timing
Signal
FS defines the frame boundaries by being asserted at a rate of 8 kHz. The duration of FS is
defined by the setup and hold times around the falling edge of PCLK and can be extended to multiple
PCLK cycles. The timing relationship between
FS and PCLK is determined by the rising edge of FS and
the first falling edge of PCLK that follows the
FS rising edge. PCLK and FS are common to all devices
connected to the PCM highway. The ratio of PCLK frequency to
FS frequency determines the number of
bit slots available during a frame, i.e., the number of bits per frame. The number of bit slots divided by 8
is the number of 8-bit time slots available during the frame.
PCLK Frequency
= Bits per Frame
Bits per Frame
= Number of Time Slots per Frame
FS Frequency (8 kHz)
8-bits per Time Slot
Refined granularity to the time slot can be achieved by programming the clock slot offset. The clock slot
defines an offset in terms of the number of bits from the start of the time slot. The combination of the
transmit and receive time slot and clock slot registers determines the bit slot at which the 73M1x66B
begins transmitting or receiving a data sample. Adjustments of a half clock period can be made using
these controls in conjunction with TPOL and RPOL.
The 73M1x66B supports a 16-bit linear transmission and receive mode. The transmission and reception
of the data samples consumes two adjacent 8-bit time slots each on the PCM highway. The 16-bit data
sample is transmitted most significant bit first starting at the bit slot defined by the TTS and TCS controls.
The transmission lasts for 16 consecutive bit slots, as illustrated in Figure 21.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 73M1966B-DB-C | 功能描述:網(wǎng)絡(luò)開發(fā)工具 73M1966B Demo Brd w/GUI Cable RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| 73M1966B-EVM | 功能描述:網(wǎng)絡(luò)開發(fā)工具 73M1966 Demo Brd & MotherBrd RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| 73M1966B-IM/F | 制造商:Maxim Integrated Products 功能描述: |
| 73M1966B-KEYCHN | 功能描述:網(wǎng)絡(luò)開發(fā)工具 Keychain Eval Module RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| 73M1AR0015F | 功能描述:RES 0.0015 OHM 1% 1W 1206 制造商:cts resistor products 系列:73M1A 包裝:帶卷（TR） 零件狀態(tài):在售 電阻值:1.5 MOhms 容差:±1% 功率（W）:1W 成分:金屬薄膜 特性:電流檢測 溫度系數(shù):±100ppm/°C 工作溫度:-55°C ~ 155°C 封裝/外殼:1206（3216 公制） 供應(yīng)商器件封裝:1206 大小/尺寸:0.126" 長 x 0.063" 寬（3.20mm x 1.60mm） 高度 - 安裝（最大值）:0.035"（0.90mm） 端子數(shù):2 故障率:- 標準包裝:4,000 |
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