參數(shù)資料
型號: 73M1966B-DB-C
廠商: Maxim Integrated Products
文件頁數(shù): 55/88頁
文件大?。?/td> 0K
描述: BOARD DEMO 73M1966B CBL 20TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
系列: *
DS_1x66B_001
73M1866B/73M1966B Data Sheet
Rev. 1.6
59
Table 36 lists the value of Receive Gain for each value of RXG.
Table 36: Receive Gain Control
RXG1
0x14[1]
RXG0
0x14[0]
Gain Nom
(dB)
0
-6.0
0
1
-3.0
1
0
0.0
1
+3.0
The precise values of the digital gain settings are:
Bit
7
6
5
4
3
2
1
0
Gain
0.25
0.5
1.5
1.25
1.125
1.0625
1.03125 1.015625
Gain / Attenuation
-12.04dB
-6.02dB
3.52dB
1.94dB
1.02dB
0.53dB
0.27dB
0.13dB
8.8.1.3 Maximum Levels
The 73M1x66B is capable of providing gain attenuation in both the digital and analog domain. It is important
to note that for optimum performance the transmitter output and receiver input should not exceed more than
+7.25 dBm. Signal levels that are greater than this will cause distortion and reduced performance.
This implies that the maximum input signal capable by the transmitter, if adjusted for unity gain, is the
+7.25 dBm, e.g. digital gain of -6.0 dB (ensures analog input is less than +1.25 dBm) and analog gain of
+6 dB gives +7.25 dBm.
8.8.2
Time Slot Assignment Example
Figure 31 shows an example of the timing of transmit and receive time slots with changes in the time slot,
clock slot and edge controls. Refer to Section 8.8, PCM Control Functions.
To program the first transmit time slot after
FS, TTC=31, TCS=7 and TPOL=1:
The first receive time slot after
FS would be RTS=31, RCS=7 and RPOL=0.
Adjustments of clock period can be made using these registers.
FS
PCLK
DR
RTS, RCS = 0, 0
RPOL=0
RTS, RCS = 0, 0
RPOL=1
RTS, RCS = 31, 7
RPOL=0
RTS, RCS = 31, 7
RPOL=1
DX
TTS, TCS = 0, 0
TPOL=1
TTS, TCS = 0, 0
TPOL=0
TTS, TCS = 31, 7
TPOL=0
TTS, TCS = 31, 7
TPOL=1
Figure 31: Timing Relationships with Various TTS, TCS, TPOL, and RTS, RCS, RPOL Settings
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