參數(shù)資料
型號(hào): 71V67703S75BQ
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 256K X 36 CACHE SRAM, 7.5 ns, PBGA165
封裝: 13 X 15 MM, 1.2 MM HEIGHT, 1 MM PITCH, FBGA-165
文件頁(yè)數(shù): 9/23頁(yè)
文件大?。?/td> 515K
代理商: 71V67703S75BQ
6.42
17
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
tC
Y
C
tS
S
tC
L
tC
H
tH
A
tS
A
tS
C
tH
C
tO
E
tO
LZ
tH
S
C
LK
A
D
S
P
A
D
S
C
A
D
R
E
S
G
W
C
E
,C
S
1
A
D
V
D
A
T
A
O
U
T
O
E
Z
S
in
gle
R
ea
d
S
no
oz
e
M
od
e
tZ
Z
P
W
530
9
dr
w
13
O
1(
A
x)
A
x
(N
ote
4)
tZ
Z
R
A
z
,
NOTES:
1.
Device
must
power
up
in
deselected
Mode.
2.
LBO
is
Don't
Care
for
this
cycle.
3.
It
is
not
necessary
to
retain
the
state
of
the
input
registers
throughout
the
Power-down
cycle.
4.
CS
0timing
transitions
are
identical
but
inverted
to
the
CE
and
CS
1signaals.
For
example,
when
CE
and
CS
1are
LOW
on
this
waveform,
CS
0is
HIGH.
Timing Waveform of Sleep (ZZ) and Power-Down Modes (1,2,3)
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