參數(shù)資料
型號(hào)： 71V67703S75BQ
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： SRAM
英文描述： 256K X 36 CACHE SRAM, 7.5 ns, PBGA165
封裝： 13 X 15 MM, 1.2 MM HEIGHT, 1 MM PITCH, FBGA-165
文件頁(yè)數(shù)： 12/23頁(yè)
文件大?。?/td> 515K
代理商： 71V67703S75BQ
6.42
2
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Symbol
Pin Function
I/O
Active
Description
A0-A18
Address Inputs
I
N/A
Synchronous Address inputs. The address register is trigge red by a combi-nation of the
rising e dge of CLK and
ADSC Low or ADSP Low and CE Low.
ADSC
Address Status
(Cache Controller)
I
LOW
Synchronous Address Status from Cache Controller.
ADSC is an active LOW input that is
used to load the address registers with new addresses.
ADSP
Address Status
(Processor)
I
LOW
Synchronous Address Status from Processor.
ADSP is an active LOW input that is used to
load the address registers with new addresses.
ADSP is gated by CE.
ADV
Burst Address
Advance
I
LOW
Synchronous Address Advance.
ADV is an active LOW input that is used to advance the
internal burst counter, controlling burst access after the initial address is loaded. When the
inp ut is HIGH the burst counter is not incremented; that is, there is no address advance.
BWE
Byte Write Enable
I
LOW
Synchronous byte write enable gates the byte write inputs
BW1-BW4. If BWE is LOW at the
rising ed ge of CLK then
BWx inputs are passed to the next stage in the circuit. If BWE is
HIGH then the byte write inputs are blocked and only
GW can initiate a write cycle.
BW1-BW4
Individual Byte
Write Enables
I
LOW
Synchronous byte write enables.
BW1 controls I/O0-7, I/OP1, BW2 controls I/O8-15, I/OP2, etc.
Any active byte write cause s all outputs to be disabled.
CE
Chip Enable
I
LOW
Synchronous chip enable.
CE is used with CS0 and CS1 to enable the IDT71V67703/7903.
CE also gates ADSP.
CLK
Clock
I
N/A
This is the clock input. All timing references for the device are made with respect to this
input.
CS0
Chip Select 0
I
HIGH
Synchronous active HIGH chip select. CS0 is used with
CE and CS1 to enable the chip.
CS1
Chip Select 1
I
LOW
Synchrono us active LOW chip select.
CS1 is used with CE and CS0 to enable the chip.
GW
Global Write
Enable
I
LOW
Synchronous global write enable. This input will write all four 9-bit data bytes when LOW
on the rising edge of CLK.
GW supersedes individual byte write enables.
I/O0-I/O31
I/OP1-I/OP4
Data Input/Output
I/O
N/A
Synchronous data input/output (I/O) pins. The data input path is registered, triggered by
the rising edge of CLK. The data output path is flow-through (no output register).
LBO
Linear Burst Order
I
LOW
Asynchro nous burst order selection input. When
LBO is HIGH, the inter-leaved burst
sequence is selected. When
LBO is LOW the Linear burst sequence is selected. LBO is a
static input and must not change state while the device is operating.
OE
Output Enable
I
LOW
Asynchronous output enable. When
OE is LOW the data output drivers are enabled on the
I/O pins if the chip is also selected. When
OE is HIGH the I/O pins are in a high-
impedance state.
VDD
Power Supply
N/A
3.3V core power supply.
VDDQ
Power Supply
N/A
3.3V I/O Supply.
VSS
Ground
N/A
Ground.
NC
No Connect
N/A
NC pins are not electrically connected to the device.
ZZ
Sleep Mode
1
HIGH
Asynchronous sleep mode input. ZZ HIGH will g ate the CLK internally and power down
the IDT71V67703/7903 to its lowest power consump tion level. Data retention is guaranteed
in Sleep Mode.
5309 tbl 02
Pin Definitions(1)
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
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