參數(shù)資料
型號: 71V67703S75BQ
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 256K X 36 CACHE SRAM, 7.5 ns, PBGA165
封裝: 13 X 15 MM, 1.2 MM HEIGHT, 1 MM PITCH, FBGA-165
文件頁數(shù): 10/23頁
文件大?。?/td> 515K
代理商: 71V67703S75BQ
6.42
18
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
NOTES:
1. ZZ input is LOW,
ADV is HIGH and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. For read cycles,
ADSP and ADSC function identically and are therefore interchangable.
Non-Burst Read Cycle Timing Waveform
CLK
AD SP
GW
, BW E, BW x
CE
, CS1
CS0
ADDRESS
AD SC
DATAOUT
OE
Av
Aw
Ax
Ay
Az
(Av)
(Aw)
(Ax)
(Ay)
5309 drw 10
,
Non-Burst Write Cycle Timing Waveform
CLK
AD SP
GW
CE
, CS1
CS0
ADDRESS
AD SC
DATAIN
Av
Aw
Ax
Az
Ay
(Av)
(Aw)
(Ax)
(Az)
(Ay)
5309 drw 11
,
NOTES:
1. ZZ input is LOW,
ADV and OE are HIGH, and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. Although only
GW writes are shown, the functionality of BWE and BWx together is the same as GW.
4. For write cycles,
ADSP and ADSC have different limitations.
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