參數(shù)資料
型號(hào): 71V67703S75BQ
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): SRAM
英文描述: 256K X 36 CACHE SRAM, 7.5 ns, PBGA165
封裝: 13 X 15 MM, 1.2 MM HEIGHT, 1 MM PITCH, FBGA-165
文件頁(yè)數(shù): 4/23頁(yè)
文件大?。?/td> 515K
代理商: 71V67703S75BQ
6.42
12
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics (VDD = 3.3V ±5%, Commercial and Industrial
Temperature Ranges)
7.5ns
8ns
8.5ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Clock Parameter
tCYC
Clock Cycle Time
8.5
____
10
____
11.5
____
ns
tCH
(1)
Clock High Pulse Width
3
____
4
____
4.5
____
ns
tCL
(1)
Clock Low Pulse Width
3
____
4
____
4.5
____
ns
Output Parameters
tCD
Clock High to Valid Data
____
7.5
____
8
____
8.5
ns
tCDC
Clock High to Data Change
2
____
2
____
2
____
ns
tCLZ
(2)
Clock High to Output Active
0
____
0
____
0
____
ns
tCHZ
(2)
Clock High to Data High-Z
2
3.5
2
3.5
2
3.5
ns
tOE
Output Enable Access Time
____
3.5
____
3.5
____
3.5
ns
tOLZ
(2)
Output Enable Low to Output Active
0
____
0
____
0
____
ns
tOHZ
(2)
Outp ut Enable High to Output High-Z
____
3.5
____
3.5
____
3.5
ns
Set Up Times
tSA
Address Setup Time
1.5
____
2
____
2
____
ns
tSS
Address Status Setup Time
1.5
____
2
____
2
____
ns
tSD
Data In Setup Time
1.5
____
2
____
2
____
ns
tSW
Write Setup Time
1.5
____
2
____
2
____
ns
tSAV
Address Advance Setup Time
1.5
____
2
____
2
____
ns
tSC
Chip Enable/Select Setup Time
1.5
____
2
____
2
____
ns
Hold Times
tHA
Address Hold Time
0.5
____
0.5
____
0.5
____
ns
tHS
Address Status Hold Time
0.5
____
0.5
____
0.5
____
ns
tHD
Data In Hold Time
0.5
____
0.5
____
0.5
____
ns
tHW
Write Hold Time
0.5
____
0.5
____
0.5
____
ns
tHAV
Address Advance Hold Time
0.5
____
0.5
____
0.5
____
ns
tHC
Chip Enable/Select Hold Time
0.5
____
0.5
____
0.5
____
ns
Sleep Mode and Configuration Parameters
tZZPW
ZZ Pulse Width
100
____
100
____
100
____
ns
tZZR(3)
ZZ Recovery Time
100
____
100
____
100
____
ns
tCFG(4)
Configuration Set-up Time
34
____
40
____
50
____
ns
5309 tbl 16
NOTES:
1. Measured as HIGH above VIH and LOW below VIL.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the
LBO input. LBO is a static input and must not change during normal operation.
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