參數(shù)資料
型號： 71V3557SA75BGI8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： SRAM
英文描述： 128K X 36 ZBT SRAM, 7.5 ns, PBGA119
封裝： 14 X 22 MM, PLASTIC, BGA-119
文件頁數(shù)： 7/28頁
文件大?。?/td> 511K
代理商： 71V3557SA75BGI8
6.42
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
15
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V +/-5%)
Figure 2. Lumped Capacitive Load, Typical Derating
Figure 1. AC Test Load
AC Test Loads
AC Test Conditions (VDDQ = 3.3V)
DC Electrical Characterics Over the Operating
Temperature and Supply Voltage Range (1) (VDD = 3.3V +/-5%)
NOTE:
1. The
LBO, JTAG and ZZ pins will be internally pulled to VDD and ZZ will be internally pulled to VSS if it is not actively driven in the application.
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.
VDDQ/2
50
I/O
Z0 =50
5282 drw 04
,
1
2
3
4
20 30 50
100
200
tCD
(Typical, ns)
Capacitance (pF)
80
5
6
5282 drw 05
,
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
|ILI|
Input Leakage Current
VDD = Max., VIN = 0V to VDD
___
5 A
|ILI|
LBO, JTAG and ZZ Input Leakage Current(1)
VDD = Max., VIN = 0V to VDD
___
30
A
|ILO|
Output Leakage Current
VOUT = 0V to VCC
___
5 A
VOL
Output Low Voltage
IOL = +8mA, VDD = Min.
___
0.4
V
VOH
Output High Voltage
IOH = -8mA, VDD = Min.
2.4
___
V
5282 tbl 21
Symbol
Parameter
Test Conditions
7.5ns
8ns
8.5ns
Unit
Com'l Only
Com'l
Ind
Com'l
Ind
IDD
Operating Power
Supply Current
Device Selected, Outputs Open,
ADV/
LD = X, VDD = Max.,
VIN > VIH or < VIL, f = fMAX(2)
275
250
260
225
235
mA
ISB1
CMOS Standby Power
Supply Current
Device Deselected, Outputs Open,
VDD = Max., VIN > VHD or < VLD,
f = 0(2,3)
40
45
40
45
mA
ISB2
Clock Running Power
Supply Current
Device Deselected, Outputs Open,
VDD = Max., VIN > VHD or < VLD,
f = fMAX(2,3)
105
100
110
95
105
mA
ISB3
Idle Power
Supply Current
Device Selected, Outputs Open,
CEN > VIH, VDD = Max.,
VIN > VHD or < VLD, f = fMAX
(2,3)
40
45
40
45
mA
5282 tbl 22
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
0 to 3V
2ns
1.5V
Figure 1
5282 tbl 23
相關(guān)PDF資料
PDF描述
71V3557SA85BG8 128K X 36 ZBT SRAM, 8.5 ns, PBGA119
71V67703S75BQ 256K X 36 CACHE SRAM, 7.5 ns, PBGA165
72-30-33 0 MHz - 4000 MHz RF/MICROWAVE FIXED ATTENUATOR
72-40-43 0 MHz - 4000 MHz RF/MICROWAVE FIXED ATTENUATOR
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