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參數(shù)資料
| 型號： | 71V3557SA75BGI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 128K X 36 ZBT SRAM, 7.5 ns, PBGA119 |
| 封裝： | 14 X 22 MM, PLASTIC, BGA-119 |
| 文件頁數(shù)： | 5/28頁 |
| 文件大?。?/td> | 511K |
| 代理商： | 71V3557SA75BGI8 |
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6.42
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
13
Read Operation with Clock Enable Used (1)
Write Operation with Clock Enable Used (1)
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2.
CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2.
CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Cycle
Address
R/
W
ADV/
LD
CE1(2)
CEN
BWx
OE
I/O
Comments
nA0
H
L
X
AddressA0 and Control meet setup
n+1
X
H
X
Clock n+1 Ignored
n+2
A1
HL
L
X
L
Q0
Address A0 Read out, Load A1
n+3
X
H
X
L
Q0
Clock Ignored. Data Q0 is on the bus.
n+4
X
H
X
L
Q0
Clock Ignored. Data Q0 is on the bus.
n+5
A2
HL
L
X
L
Q1
Address A1 Read out, Load A2
n+6
A3
HL
L
X
L
Q2
Address A2 Read out, Load A3
n+7
A4
HL
L
X
L
Q3
Address A3 Read out, Load A4
5282 tbl 17
Cycle
Address
R/
W
ADV/
LD
CE1(2)
CEN
BWx
OE
I/O
Comments
nA0
L
X
Address A0 and Control meet setup.
n+1
X
H
X
Clock n+1 Ignored.
n+2
A1
LL
L
X
D0
Write data D0, Load A1.
n+3
X
H
X
Clock Ignored.
n+4
X
H
X
Clock Ignored.
n+5
A2
LL
L
X
D1
Write Data D1, Load A2
n+6
A3
LL
L
X
D2
Write Data D2, Load A3
n+7
A4
LL
L
X
D3
Write Data D3, Load A4
5282 tbl 18
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