參數(shù)資料
型號： 71V3557SA75BGI8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： SRAM
英文描述： 128K X 36 ZBT SRAM, 7.5 ns, PBGA119
封裝： 14 X 22 MM, PLASTIC, BGA-119
文件頁數(shù)： 4/28頁
文件大?。?/td> 511K
代理商： 71V3557SA75BGI8
6.42
12
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Read Operation (1)
Burst Write Operation (1)
Burst Read Operation (1)
Write Operation (1)
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2.
CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2.
CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2.
CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2.
CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Cycle
Address
R/
W
ADV/
LD
CE1(2)
CEN
BWx
OE
I/O
Comments
nA0
H
L
X
Address and Control meet setup
n+1
X
XXX
L
Q0
Contents of Address A0 Read Out
5282 tbl 13
Cycle
Address
R/
W
ADV/
LD
CE1(2)
CEN
BWx
OE
I/O
Comments
nA0
H
L
X
Address and Control meet setup
n+1
X
H
X
L
X
L
Q0
Address A0 Read Out, Inc. Count
n+2
X
H
X
L
X
L
Q0+1
Address A0+1 Read Out, Inc. Count
n+3
X
H
X
L
X
L
Q0+2
Address A0+2 Read Out, Inc. Count
n+4
X
H
X
L
X
L
Q0+3
Address A0+3 Read Out, Load A1
n+5
A1
HL
L
X
L
Q0
Address A0 Read Out, Inc. Count
n+6
X
H
X
L
X
L
Q1
Address A1 Read Out, Inc. Count
n+7
A2
HL
L
X
L
Q1+1
Address A1+1 Read Out, Load A2
5282 tbl 14
Cycle
Address
R/
W
ADV/
LD
CE1(2)
CEN
BWx
OE
I/O
Comments
nA0
L
X
Address and Control meet setup
n+1
X
L
X
D0
Write to Address A0
5282 tbl 15
Cycle
Address
R/
W
ADV/
LD
CE1(2)
CEN
BWx
OE
I/O
Comments
nA0
L
X
Address and Control meet setup
n+1
X
H
X
L
X
D0
Address A0 Write, Inc. Count
n+2
X
H
X
L
X
D0+1
Address A0+1 Write, Inc. Count
n+3
X
H
X
L
X
D0+2
Address A0+2 Write, Inc. Count
n+4
X
H
X
L
X
D0+3
Address A0+3 Write, Load A1
n+5
A1
LL
L
X
D0
Address A0 Write, Inc. Count
n+6
X
H
X
L
X
D1
Address A1 Write, Inc. Count
n+7
A2
LL
L
X
D1+1
Address A1+1 Write, Load A2
5282 tbl 16
相關PDF資料
PDF描述
71V3557SA85BG8 128K X 36 ZBT SRAM, 8.5 ns, PBGA119
71V67703S75BQ 256K X 36 CACHE SRAM, 7.5 ns, PBGA165
72-30-33 0 MHz - 4000 MHz RF/MICROWAVE FIXED ATTENUATOR
72-40-43 0 MHz - 4000 MHz RF/MICROWAVE FIXED ATTENUATOR
72-10-14 0 MHz - 4000 MHz RF/MICROWAVE FIXED ATTENUATOR
相關代理商/技術(shù)參數(shù)
參數(shù)描述
71V3558S100PFG 功能描述:靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
71V3558S100PFG8 功能描述:靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
71V3558S100PFGI 功能描述:靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
71V3558S100PFGI8 功能描述:靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
71V3558S133BG 制造商:Integrated Device Technology Inc 功能描述:4.5MBIT SRAM CHIP SYNC SINGLE 3.3V 256K X 18 4.2NS - Trays 制造商:Integrated Device Technology Inc 功能描述:IDT 71V3558S133BG, 4.5MBit SRAM Chip Sync Single 3.3V 256K x 18 4.2ns 119-Pin BGA
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*