參數(shù)資料
型號: 70V659S10DR
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 128K X 36 DUAL-PORT SRAM, 10 ns, PQFP208
封裝: 28 X 28 MM, 3.50 MM HEIGHT, PLASTIC, QFP-208
文件頁數(shù): 9/24頁
文件大?。?/td> 316K
代理商: 70V659S10DR
17
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)(1)
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing (M/S = VIH)(1)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
4869 drw 14
ADDR"A"
and "B"
ADDRESSES MATCH
CE"A"
CE"B"
BUSY"B"
tAPS
tBAC
tBDC
(2)
4869 drw 15
ADDR"A"
ADDRESS "N"
ADDR"B"
BUSY"B"
tAPS
tBAA
tBDA
(2)
MATCHING ADDRESS "N"
70V659/58/57S10
Com'l Only
70V659/58/57S12
Com'l
& Ind
70V659/58/57S15
Com'l
& Ind
Symbol
Parameter
Min.
Max.Min.Max.Min.Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
____
0
____
0
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
ns
tINS
Interrupt Set Time
____
10
____
12
____
15
ns
tINR
Interrupt Reset Time
____
10
____
12
____
15
ns
4869 tbl 15
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