參數(shù)資料
型號: 70V659S10DR
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 128K X 36 DUAL-PORT SRAM, 10 ns, PQFP208
封裝: 28 X 28 MM, 3.50 MM HEIGHT, PLASTIC, QFP-208
文件頁數(shù): 4/24頁
文件大?。?/td> 316K
代理商: 70V659S10DR
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
12
Timing of Power-Up Power-Down
Waveform of Read Cycles(5)
NOTES:
1. Timing depends on which signal is asserted last, OE, CE or BEn.
2. Timing depends on which signal is de-asserted first CE, OE or BEn.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
tRC
R/
W
CE
ADDR
tAA
OE
BEn
4869 drw 06
(4)
tACE
(4)
tAOE
(4)
tABE
(4)
(1)
tLZ
tOH
(2)
tHZ
(3,4)
tBDD
DATAOUT
BUSYOUT
VALID DATA
(4)
(6)
CE
4869 drw 07
tPU
ICC
ISB
tPD
50%
.
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