參數(shù)資料
型號(hào)： 70V659S10DR
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： SRAM
英文描述： 128K X 36 DUAL-PORT SRAM, 10 ns, PQFP208
封裝： 28 X 28 MM, 3.50 MM HEIGHT, PLASTIC, QFP-208
文件頁(yè)數(shù)： 8/24頁(yè)
文件大?。?/td> 316K
代理商： 70V659S10DR
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
16
Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)(2,4,5)
Timing Waveform of Write with BUSY (M/S = VIL)
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the 'slave' version.
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
4869 drw 12
tDW
tAPS
ADDR"A"
tWC
DATAOUT "B"
MATCH
tWP
R/
W"A"
DATAIN "A"
ADDR"B"
tDH
VALID
(1)
MATCH
BUSY"B"
tBDA
VALID
tBDD
tDDD
(3)
tWDD
tBAA
.
4869 drw 13
R/
W"A"
BUSY"B"
tWB
(3)
R/
W"B"
tWH
(1)
(2)
tWP
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70V659S10DRG 功能描述:IC SRAM 4MBIT 208QFP 制造商:idt, integrated device technology inc 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:6
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70V659S12BC8 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Async Dual 3.3V 4.5M-Bit 128K x 36 12ns 256-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM ASYNC DUAL 3.3V 4.5MBIT 128KX36 12NS 256BGA - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:128Kx36 STD-PWR 3.3V DUAL-PORT RAM
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