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參數(shù)資料
| 型號(hào)： | 68HC705BD7 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 中文描述： | 8位微控制器單元（MCU）。（8位微控制器） |
| 文件頁數(shù)： | 68/85頁 |
| 文件大?。?/td> | 302K |
| 代理商： | 68HC705BD7 |
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MOTOROLA
Page 58
SECTION 11: MULTI-FUNCTION TIMER
GENERAL RELEASE SPECIFICATION
MC68HC05BD7 Rev. 2.0
PRELMNARY
count of the divide-by-64 counter is hence 63 rather than 64.
RT1, RT0 should only be changed right after COP timer has
been reset; otherwise, unpredictable result will occur.
$FF to $00. A CPU interrupt request will be generated if
TOFIE is set. TOF is a clearable, read-only status bit. Clearing
the TOF is done by writing a ’0’ to TOF.
Real Time Interrupt Flag indicates if the output of the RTI
circuit goes active. The clock frequency that drives the RTI
circuit is E/2,048, giving a maximum interrupt period of 1.024
milliseconds at a bus rate of 2 MHz. A CPU interrupt request
will be generated if RTIE is set. RTIF is a clearable, read-only
status bit. Clearing the RTIF is done by writing a ’0’ to RTIF.
When Timer Over Flow Interrupt Enable (TOFIE) bit is set, the
TOF flag is enabled to generate an interrupt request to the
generating an interrupt request.
When Real Time Interrupt Enable (RTIE) is set, the RTIF flag
is enabled to generate an interrupt request to the CPU. When
RTIE is cleared, the RTIF flag is prevented from generating an
interrupt request.
0 = Both level and edge triggering are detected for external
interrupt (IRQ).
1 = Only edge triggering is detected for external interrupt.
The INHibit IRQ bit will inhibit the external interrupt input.
When it is set, no active falling edge or low period will be
recognized as interrupt request. It is possible for a low state
input on the IRQ pin to be seen as a falling edge event when
the INHIRQ bit changes from one to zero, see
Figure 4-2
for
reference. Reset clears this bit.
These two bits are used to define real time interrupt rate as
well as COP reset rate as tabulated in
Table 11-1
. Reset sets
these two bits for the slowest watchdog reset rate. Note that
the minimal COP reset period is determined by dividing the
COP master clock, which is the real time interrupt clock, by
63(63=64-1). The reason is that COP reset operation is
asynchronous to COP master clock edge. Therefore it is
possible that right after COP reset operation, a COP master
RTIF
bit 6
TOFIE
bit 5
RTIE
bit 4
IRQN
bit 3
INHIRQ
bit 2
RT1-0
bit 1,0
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