- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369230 > 68HC705BD7 (Motorola, Inc.) 8-Bit Microcontroller Units (MCU).(8位微控制器) PDF資料下載
參數(shù)資料
| 型號： | 68HC705BD7 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 中文描述： | 8位微控制器單元（MCU）。（8位微控制器） |
| 文件頁數(shù)： | 34/85頁 |
| 文件大?。?/td> | 302K |
| 代理商： | 68HC705BD7 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁當(dāng)前第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁
MOTOROLA
Page 24
SECTION 4: INTERRUPTS
GENERAL RELEASE SPECIFICATION
MC68HC05BD7 Rev. 2.0
PRELMNARY
interrupt will vector to the interrupt service routine located at the address specified by the
contents of $3FF8 and $3FF9. The VSYNC Interrupt Flag (VSIF) must be cleared by writing
’0’ to it in the interrupt routine.
the interrupt service routine plus 21 cycles. Once a pulse occurs, the next pulse should not
occur until the MCU software has exited the routine (an RTI occurs). The second
configuration shows several interrupt line “wire-ANDed” to perform the interrupts at the
processor. Thus, if after servicing one interrupt and the interrupt line remains low, then the
next interrupt is recognized.
NOTE:
IRQN is located at bit 3 of the Multi-function Timer Register at $0008, and
is cleared by reset.
Figure 4-2: External Interrupt
4.4.2
VSYNC Interrupt
The VSYNC interrupt is generated when a specific edge of VSYNC input is detected as
described in
SECTION 10
. The interrupt enable bit, VSIE, for the VSYNC interrupt is
located at bit 7 of SYNC Processor Control and Status Register (SPCSR) at $000C. The I-
bit in the CCR must be cleared in order for the VSYNC interrupt to be enabled. This
4.4.3
DDC12AB Interrupt
The DDC12AB interrupt is generated by the DDC12AB circuit as described in
SECTION 9
.
The interrupt enable bit for the DDC12AB interrupt is located at bit 6 of DDC12AB Control
Register (DCR) at $0018. The I-bit in the CCR must be cleared in order for the DDC12AB
interrupt to be enabled. This interrupt will vector to the interrupt service routine located at
the address specified by the contents of $3FF6 and $3FF7.
IRQ
IRQ1
IRQn
IRQ
(MCU)
t
ILIH
t
ILIL
t
ILIH
The mnimumpulse width tILIH is one
internal bus period.
The period tILIL should not be less than the
number of cycles it takes to execute the
interrupt service routine plus 21 cycles
Level-sensitive Trigger Condition
If after servicing an interrupt, the IRQ
remains low, then the next interrupt is
recognized.
Normally used with pull-up resistor for
Wire-Ored connection
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 68HC05J5A | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 68HC705J5A | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 68HRC05J5A | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 68HRC705J5A | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 68HC05K0 | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 68HC705C5 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:SPECIFICATION(General Release) |
| 68HC705C8 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:PROGRAMMING REFRERENCE GUIDE |
| 68HC705C8ACP | 制造商: 功能描述: 制造商:Motorola Inc 功能描述: 制造商:undefined 功能描述: |
| 68HC705CJ4FB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| 68HC705CJ4P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。