參數(shù)資料
型號(hào)： 48e30
廠商： Holtek Semiconductor Inc.
英文描述： 8-Bit I/O Type MCU (With EEPROM)
中文描述： 8位I / O型微控制器（帶EEPROM）
文件頁(yè)數(shù)： 41/44頁(yè)
文件大小： 351K
代理商： 48E30
HT48E30
Rev. 0.00
6
January 12, 2004
Preliminary
Functional Description
Execution Flow
The HT48E30 system clock is derived from either a
crystal or an RC oscillator and is internally divided into
four non-overlapping clocks. One instruction cycle con-
sists of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while de-
coding and execution takes the next instruction cycle.
This pipelining scheme ensures that instructions are ef-
fectively executed in one cycle. If an instruction changes
the contents of the program counter, two cycles are re-
quired to complete the instruction.
Program Counter
- PC
The program counter (PC) controls the sequence in
which the instructions stored in the program ROM are
executed and its contents specify a full range of pro-
gram memory.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
incremented by one. The program counter then points to
the memory word containing the next instruction code.
When executing a jump instruction, conditional skip ex-
ecution, loading into the PCL register, subroutine call or
return from subroutine, initial reset, internal interrupt,
external interrupt or return from interrupt, the PC manip-
ulates the program transfer by loading the address cor-
responding to each instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed with the next instruction.
The lower byte of the program counter (PCL) is a read-
able and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within the current program ROM page.
When a control transfer takes place, an additional
dummy cycle is required.
Mode
Program Counter
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
00000000000
External Interrupt
00000000100
Timer/Event Counter Overflow
00000001000
Skip
PC+2
Loading PCL
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note: *10~*0: Program counter bits
S10~S0: Stack register bits
#10~#0: Instruction code bits
@7~@0: PCL bits
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
F e t c h I N S T ( P C )
E x e c u t e I N S T ( P C - 1 )
F e t c h I N S T ( P C + 1 )
E x e c u t e I N S T ( P C )
F e t c h I N S T ( P C + 2 )
E x e c u t e I N S T ( P C + 1 )
P C
P C + 1
P C + 2
S y s t e m C l o c k
O S C 2 ( R C o n l y )
P C
Execution Flow
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