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參數(shù)資料
| 型號： | 48e30 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 8-Bit I/O Type MCU (With EEPROM) |
| 中文描述： | 8位I / O型微控制器（帶EEPROM） |
| 文件頁數(shù)： | 10/44頁 |
| 文件大?。?/td> | 351K |
| 代理商： | 48E30 |
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HT48E30
Rev. 0.00
18
January 12, 2004
Preliminary
The EEPROM data memory is accessed via a
three-wire serial communication interface by writing to
EECR. It is arranged into 128 words by 8 bits. The
EEPROM data memory contains seven instructions:
READ, ERASE, WRITE, EWEN, EWDS, ERAL and
WRAL. These instructions are all made up of 10 bits
data: 1 start bit, 2 op-code bits and 7 address bits.
By writing CS, SK and DI, these instructions can be
given to the EEPROM. These serial instruction data pre-
sented at the DI will be written into the EEPROM data
memory at the rising edge of SK. During the READ cy-
cle, DO acts as the data output and during the WRITE or
ERASE cycle, DO indicates the BUSY/READY status.
When the DO is active for read data or as a BUSY/
READY indicator the CS pin must be high; otherwise
DO will be in a high state. For successful instructions,
CS must be low once after the instruction is sent. After
power on, the device is by default in the EWDS state.
And, an EWEN instruction must be performed before
any ERASE or WRITE instruction can be executed.
C S
S K
D O
D I
t C D S
t C S S
t C S H
t S K L
t S K H
t D I S
t D I H
t P D 1
t P D 0
V a l i d D a t a
1
The following are the functional descriptions and timing diagrams of all seven instructions.
EECR A.C. Characteristics
Ta=25
°C
Symbol
Parameter
VCC=5V
±10%
VCC=2.2V
±10%
Unit
Min.
Max.
Min.
Max.
fSK
Clock Frequency
0201
MHz
tSKH
SK High Time
250
500
ns
tSKL
SK Low Time
250
500
ns
tCSS
CS Setup Time
50
100
ns
tCSH
CS Hold Time
0
0
ns
tCDS
CS Deselect Time
250
250
ns
tDIS
DI Setup Time
100
200
ns
tDIH
DI Hold Time
100
200
ns
tPD1
DO Delay to
1
250
500
ns
tPD0
DO Delay to
0
250
500
ns
tSV
Status Valid Time
250
250
ns
tHZ
DO Disable Time
100
200
ns
tPR
Write Cycle Time Per Word
2
5ms
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