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參數(shù)資料
| 型號： | 48e30 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 8-Bit I/O Type MCU (With EEPROM) |
| 中文描述： | 8位I / O型微控制器（帶EEPROM） |
| 文件頁數(shù)： | 3/44頁 |
| 文件大?。?/td> | 351K |
| 代理商： | 48E30 |
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HT48E30
Rev. 0.00
11
January 12, 2004
Preliminary
tem clock is stopped, the oscillator still works within a
period of 65
ms at 5V. The WDT oscillator can be dis-
abled by options to conserve power.
Watchdog Timer
- WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator), instruction clock (system
clock divided by 4), determines the options. This timer is
designed to prevent a software malfunction or sequence
from jumping to an unknown location with unpredictable
results. The Watchdog Timer can be disabled by op-
tions. If the Watchdog Timer is disabled, all the execu-
tions related to the WDT result in no operation.
Once the internal WDT oscillator (RC oscillator with a
period of 65
ms at 5V normally) is selected, it is first di-
vided by 256 (8-stage) to get the nominal time-out pe-
riod of 18.6ms at 5V. This time-out period may vary with
temperatures, VDD and process variations. By invoking
the WDT prescaler, longer time-out periods can be real-
ized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the
WDTS) can give different time-out periods. If WS2, WS1,
and WS0 are all equal to 1, the division ratio is up to 1:128,
and the maximum time-out period is 2.4s at 5V seconds. If
the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operates in the same
manner except that in the HALT state the WDT may stop
counting and lose its protecting purpose. In this situation
the logic can only be restarted by an external logic. The
high nibble and bit 3 of the WDTS are reserved for user
s
defined flags, which can be used to indicate some speci-
fied status.
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT will stop the system clock.
WS2
WS1
WS0
Division Ratio
000
1:1
001
1:2
010
1:4
011
1:8
1
0
1:16
1
0
1
1:32
1
0
1:64
1
1:128
WDTS Register
The WDT overflow under normal operation will initialize
a
chip reset and set the status bit TO. But in the
HALT mode, the overflow will initialize a
warm reset
and only the PC and SP are reset to zero. To clear the
contents of WDT (including the WDT prescaler), three
methods are adopted; external reset (a low level to
RES), software instruction and a
HALT instruction.
The software instruction includes
CLR WDT and the
other set
-CLR WDT1 and CLR WDT2. Of these
two types of instruction, only one can be active depend-
ing on the option
-CLR WDT times selection option.If
the
CLR WDT is selected (i.e. CLRWDT times equal
one), any execution of the
CLR WDT instruction will
clear the WDT. In the case that
CLR WDT1 and CLR
WDT2
are chosen (i.e. CLRWDT times equal two),
these two instructions must be executed to clear the
WDT; otherwise, the WDT may reset the chip as a result
of time-out.
Power Down Operation
- HALT
The HALT mode is initialized by the
HALT instruction
and results in the following...
The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is se-
lected).
The contents of the on chip RAM and registers remain
unchanged.
WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT os-
cillator).
All of the I/O ports maintain their original status.
The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow per-
forms a
warm reset. After the TO and PDF flags are
examined, the reason for chip reset can be determined.
The PDF flag is cleared by a system power-up or exe-
cuting the
CLR WDT instruction and is set when exe-
cuting the
HALT instruction. The TO flag is set if a
WDT time-out occurs, and causes a wake-up that only
resets the PC and SP; the others remain in their original
status.
S y s t e m C l o c k / 4
8 - b i t C o u n t e r
W D T P r e s c a l e r
7 - b i t C o u n t e r
8 - t o - 1 M U X
W D T T i m e - o u t
W S 0 ~ W S 2
O p t i o n
S e l e c t
W D T
O S C
Watchdog Timer
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