參數(shù)資料
型號(hào)： 440GRX
廠商： Applied Micro Circuits Corp.
英文描述： PowerPC 440GRx Embedded Processor
中文描述： 嵌入式處理器的PowerPC 440GRx
文件頁(yè)數(shù)： 83/88頁(yè)
文件大小： 603K
代理商： 440GRX
440GRx – PPC440GRx Embedded Processor
Preliminary Data Sheet
84
AMCC Proprietary
Revision 1.08 – October 15, 2007
Table 25. I/O Timing—DDR SDRAM TDS
Notes:
1. All of the DQS signals are referenced to MemClkOut with the DQS delay line programmed to 1 cycle.
2. Clock speed is 166MHz.
Signal Name
TDS (ns)
Minimum
Maximum
DQS0
0.030
+0.650
DQS1
0.030
+0.620
DQS2
0.050
+0.580
DQS3
0.110
+0.480
DQS4
0.140
+0.410
DQS5
0.120
+0.480
DQS6
0.060
+0.580
DQS7
0.010
+0.690
DQS8
0.140
+0.420
Table 26. I/O Timing—DDR SDRAM TSK, TSA, and THA
Notes:
1. Clock speed is 166MHz. TSK is referenced to MemClkOut falling edge. TSA and THA are referenced to MemClkOut rising
edge.
2. The timing in this table assumes a single registered DIMM load on the outputs. To adjust the timing for unbuffered DIMMs,
use the following values by subtracting them from TSA and adding them to TSK and THA:
5 loads adjust by 0.41ns
9 loads adjust by 1.12ns
18 loads adjust by 2.12ns
3. To obtain adjusted TSA values for lower clock frequencies, use 1/2 of the cycle time for the lower clock frequency and subtract
TSK maximum (0.5TCYC TSKmax).
4. To obtain adjusted THA values for lower clock frequencies, use 1/2 of the cycle time for the lower clock frequency and add
TSK minimum (0.5TCYC + TSKmin).
Signal Name
TSK (ns)
TSA (ns)
THA (ns)
MinimumMaximumMinimum
Minimum
MemAddr00:13
0.960
0.270
3.27
2.04
BA0:2
BankSel0:1
ClkEn
CAS
RAS
WE
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