- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄33779 > 440GRX (Applied Micro Circuits Corp.) PowerPC 440GRx Embedded Processor PDF資料下載
參數(shù)資料
| 型號： | 440GRX |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PowerPC 440GRx Embedded Processor |
| 中文描述： | 嵌入式處理器的PowerPC 440GRx |
| 文件頁數(shù)： | 79/88頁 |
| 文件大小： | 603K |
| 代理商： | 440GRX |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁當(dāng)前第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁
440GRx – PPC440GRx Embedded Processor
Preliminary Data Sheet
80
AMCC Proprietary
Revision 1.08 – October 15, 2007
DDR2/1 SDRAM I/O Specifications
The DDR2/1 SDRAM controller times its operation with the internal PLB clock signal and generates MemClkOut
from the PLB clock. The PLB clock is an internal signal that cannot be directly observed. However MemClkOut is
the same frequency as the PLB clock signal and is in phase with the PLB clock signal.
Read capture logic in the DDR controller captures read data using a delayed version of DQS and internally re-
synchronizes the data to the PLB clock.The PPC440GRx contains three independently programmable digital delay
lines (DLLs) that control the timing of the indicated signals in read and write operations:
1. DQS (with respect to MemClkOut) for write operations.
2. MemData, ECC, and DM (with respect to MemClkOut) for write operations.
3. DQS (with respect to inbound MemData) for read operations.
There is also a master delay line for calibration. Programming details can be found in the PPC440GRx Embedded
Processor Users Manual.
The signals are terminated as indicated in Figure 10 for the DDR timing data in the following sections.
The PPC440GRx uses a clock forwarding scheme in which it drives the clock to the memory devices.
Data signals are divided into eight subgroups—one for each byte lane (see Table 27 on page 85)— plus a ninth
subgroup for the ECC byte lane. These signals include MemData00:63, DQS0:8, DM0:8, and ECC0:7 signals.
Signals within a data subgroup (byte lane) should be routed together.
Command Bus Operation
The command bus (MemAddr, RAS, CAS, WE, BA, ClkEn, BankSel, MemODT) is driven 180
° out-of-phase with
MemClkOut, and has no corresponding delay line. Therefore, board designers must consider two different types of
systems: 1) registered DIMMs and 2) unbuffered DIMMs. The system clocking design must also be considered. To
avoid crosstalk, the command bus signals and the data signals should not be routed together.
Board Layout Restrictions
The paths (traces) for the data and the associated data strobe signal should be routed with the same length
between the PPC440GRx and the SDRAM devices, allowing the rising and falling edges of the strobe to arrive at
the capture logic at the same time the data is in transition. All of the following timing assumes a trace velocity of
167ps/in.
Board designs must meet the following criteria:
Skew on the signals in any byte lane should not exceed 50ps (0.3 in).
Data subgroup trace lengths must be no more than 5in. (800ps) and have a difference of no more than 2.5in.
(400ps).
Byte lane subgroup trace length must be no less than 1.25 in. (209ps).
For example, traces that average 3.00in. in length and 167ps/in., and meet the maximum 50ps skew requirement,
would have a maximum length difference of 0.3in. So, they would be between 2.85in. and 3.15in. in length.
If the above timing recommendations are followed, the package wire bond lengths can be ignored.
Clocking
Clocking skew to all DRAMs must be minimized. The maximum allowed is considered to be 10ps. Because of the
stringent requirements on DDR device clock inputs, it is expected that board designers will use some type of
external PLL suitable to redrive the clock to the DDR SDRAMs. In such a system, the PLL acts like a zero-delay
insertion buffer.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 440GR | Power PC 440GR Embedded Processor |
| 440GX | Power PC 440GX Embedded Processor |
| 440SPE | PowerPC 440SPe Embedded Processor |
| 440SP | PowerPC 440SP Embedded Processor |
| 4414-308 | 8 POS SOIC ADAPTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 440GS001NF1934-4 | 功能描述:環(huán)形MIL規(guī)格后蓋 CRIMIP RING ADPTR DC STRAIGHT RoHS:否 制造商:Amphenol PCD MIL 類型:MIL-DTL-38999 III, IV 系列:AS85049 產(chǎn)品類型:Environmental EMI/RFI Backshells 外殼類型:Straight 外殼大小:18 外殼材質(zhì):Aluminum Alloy |
| 440GS001NF2535-4 | 功能描述:環(huán)形MIL規(guī)格后蓋 CRIMIP RING ADPTR DC STRAIGHT RoHS:否 制造商:Amphenol PCD MIL 類型:MIL-DTL-38999 III, IV 系列:AS85049 產(chǎn)品類型:Environmental EMI/RFI Backshells 外殼類型:Straight 外殼大小:18 外殼材質(zhì):Aluminum Alloy |
| 440GS031B2912-4 | 制造商:Glenair Inc 功能描述:Shrink Boot Adapters 180° 29 Shell Size Olive Drab Cadmium Aluminum Direct 制造商:Glenair 功能描述:Shrink Boot Adapters 180° 29 Shell Size Olive Drab Cadmium Aluminum Direct |
| 440GS031B3314-4 | 制造商:Glenair Inc 功能描述:Shrink Boot Adapters 180° 33 Shell Size Olive Drab Cadmium Aluminum Direct 制造商:Glenair 功能描述:Shrink Boot Adapters 180° 33 Shell Size Olive Drab Cadmium Aluminum Direct |
| 440GS031NF1102-3BT | 功能描述:環(huán)形MIL規(guī)格后蓋 BND/SHRNK BOOT ADPTR DC STRT BAND BOOT RoHS:否 制造商:Amphenol PCD MIL 類型:MIL-DTL-38999 III, IV 系列:AS85049 產(chǎn)品類型:Environmental EMI/RFI Backshells 外殼類型:Straight 外殼大小:18 外殼材質(zhì):Aluminum Alloy |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。