參數(shù)資料
型號(hào)： 440GRX
廠商： Applied Micro Circuits Corp.
英文描述： PowerPC 440GRx Embedded Processor
中文描述： 嵌入式處理器的PowerPC 440GRx
文件頁(yè)數(shù)： 5/88頁(yè)
文件大?。?/td> 603K
代理商： 440GRX
440GRx – PPC440GRx Embedded Processor
Revision 1.08 – October 15, 2007
AMCC Proprietary
13
Preliminary Data Sheet
DDR2/1 SDRAM Memory Controller
The Double Data Rate 2/1 (DDR2/1) SDRAM memory controller supports industry standard discrete devices that
are compatible with both the DDR1 or DDR2 specifications. The correct I/O supply voltage must be provided for the
two types of DDR devices: DDR1 devices require +2.5V and DDR2 devices require +1.8V.
Global memory timings, address and bank sizes, and memory addressing modes are programmable.
Features include:
32-bit memory interface for DDR1
32- or 64-bit memory interface for DDR2
Optional Error Checking and Correcting (ECC)
2.6-GB/s peak data rate
Two memory banks of up to 1 GB each
Maximum capacity of 2GB
Support for 256-Mb, 512-Mb, and 1-Gb DDR devices, with CAS latencies of 2 or 3
Support for DDR266/333 and DDR2-266/333.
(Faster parts may be used but must be clocked no faster than 166MHz)
Page mode accesses (up to 16 open pages) with configurable paging policy
Programmable address mapping and timing
Software initiated self-refresh
Power management (self-refresh, suspend, sleep)
One or two chip selects
External Peripheral Bus Controller (EBC)
Features include:
Up to six ROM, EPROM, SRAM, Flash memory, and slave peripheral I/O banks supported
Up to 83MHz operation
Burst and non-burst devices
32-bit byte-addressable data bus
Data parity
30-bit address
Peripheral Device pacing with external “Ready”
Latch data on Ready, synchronous or asynchronous
Programmable access timing per device
– 256 Wait States for non-burst
– 32 Burst Wait States for first access and up to 8 Wait States for subsequent accesses
– Programmable CSon, CSoff relative to address
– Programmable OEon, WEon, WEoff (1 to 4 clock cycles) relative to CS
Programmable address mapping
External DMA Slave Support
External master interface
– Write posting from external master
– Read prefetching on PLB for external master reads
– Bursting capable from external master
– Allows external master access to all non-EBC PLB slaves
– External master can control EBC slaves for access
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