參數(shù)資料
型號： 440GRX
廠商： Applied Micro Circuits Corp.
英文描述： PowerPC 440GRx Embedded Processor
中文描述： 嵌入式處理器的PowerPC 440GRx
文件頁數(shù)： 7/88頁
文件大?。?/td> 603K
代理商： 440GRX
440GRx – PPC440GRx Embedded Processor
Revision 1.08 – October 15, 2007
AMCC Proprietary
15
Preliminary Data Sheet
IIC Bus Controller
Features include:
Two IIC interfaces provided
Support for Philips Semiconductors I2C Specification, dated 1995
Operation at 100kHz or 400kHz
8-bit data
10- or 7-bit address
Slave transmitter and receiver
Master transmitter and receiver
Multiple bus masters
Two independent 4 x 1 byte data buffers
Twelve memory-mapped, fully programmable configuration registers
One programmable interrupt request signal
Provides full management of all IIC bus protocols
Programmable error recovery
Includes an integrated bootstrap controller (BSC) that is multiplexed with the second IIC interface
Serial Peripheral Controller (SPI/SCP)
The Serial Peripheral Interface (also known as the Serial Communications Port) is a full-duplex, synchronous,
character-oriented (byte) port that allows the exchange of data with other serial devices. The SCP is a master on the
serial port supporting a 3-wire interface (receive, transmit, and clock), and is a slave on the OPB.
Features include:
Three-wire serial port interface
Full-duplex synchronous operation
SCP bus master
OPB bus slave
Programmable clock rate divider
Clock inversion
Reverse data
Local data loop back for test
NAND Flash Controller
The NAND Flash controller provides a simple interface between the EBC and up to four separate external NAND
Flash devices. It provides both direct command, address, and data access to the external device as well as a
memory-mapped linear region that generates data accesses. NAND Flash data is transferred on the peripheral data
bus.
Features include:
One to four banks supported on EBC
Direct interface to:
– Discrete NAND Flash devices (up to four devices)
– SmartMedia Card socket (22-pins)
Device sizes:
– 4MB and larger supported for read/write access
– 4MB to 256MB for boot-from-NAND flash (size supported depends on addressing mode)
(512 + 16)-B or (2K + 64)-B page sizes supported
Boot-from-NAND
– Execute up to 4KB of boot code out of first block.
– Automatic page read accesses performed based on device configuration and addressing mode.
ECC provides single-bit error correction and double-bit error detection in each 256B of stored data
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