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26
Revision 1.2
Signal Definitions (
Continued
)
G
Figure 2-3. 320 SPGA Pin Assignment Diagram
For order information, refer to Section A.1 “Order Information” on page 246.
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Q
R
S
T
U
V
AA
AB
AC
AD
AE
AF
Index Corner
27 28 29 30 31 32 33 34 35 36 37
AG
AH
AJ
AK
AL
AM
W
Y
X
Z
AN
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Q
R
S
T
U
V
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
W
Y
X
Z
AN
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
VCC3
AD25
VSS
VCC2
AD16
VCC3
STOP#
SERR#
VSS
AD11
AD8
VCC3
AD2
VCC2
VSS
TEST0
VCC3
VSS
VSS
AD27
CBE3#
AD21
AD19
CBE2#
TRDY#
LOCK#
CBE1#
AD13
AD9
AD6
AD3
SMI#
AD1
TEST2
MD33
MD2
VCC3
AD31
AD26
AD23
VCC2
AD18
FRAME#
VSS
PAR
VCC3
VSS
AD4
AD0
VCC2
IRQ13
MD1
MD34
VCC3
AD30
AD29
AD24
AD22
AD20
AD17
IRDY#
PERR#
AD14
AD12
AD7
INTR
TEST1
TEST3
MD0
MD32
MD3
MD35
REQ0#
REQ2#
AD28
VSS
VCC2
VCC2
VSS
DEVSEL#
AD15
VSS
CBE0#
AD5
VSS
VCC2
VCC2
VSS
MD4
MD36
NC
GNT0#
TDI
MD5
NC
VSS
CKMD2
VSS
VSS
MD37
VSS
SUSPA#
TDO
VSS
TEST
REQ1#
GNT1#
VCC2
VCC2
VCC2
RESET
SUSP#
VCC3
TMS
VSS
FPVSYNC
TCLK
SERIALP
VSS
NC
CKMD1
FPHSYNC
CKMD0
VID_VAL
PIX0
PIX1
PIX2
VSS
VCC3
VSS
PIX3
VID_CLK
PIX6
PIX5
PIX4
NC
PIX9
PIX8
VSS
PIX7
NC
PIX10
VCC3
PIX11
VSS
PIX12
PIX13
VCC2
VCC2
VCC2
CRTHSYNC
DCLK
PIX14
VSS
VCC2
PIX15
PIX16
VSS
PIX17
VSS
CRTVSYNC
VDAT6
MD6
MD38
VCC2
VSS
MD7
MD39
MD8
VCC2
VCC2
VCC2
MD40
MD9
VSS
MD41
VCC3
MD10
MD42
MD11
VSS
MD43
MD44
MD12
MD14
MD13
MD45
MD15
MD46
VSS
VCC3
VSS
SYSCLK
MD47
WEA#
WEB#
CASA#
DQM0
CASB#
DQM1
VSS
DQM4
CS2#
DQM5
VSS
CS0#
VCC3
RASB#
RASA#
VCC2
VCC2
VCC2
VCC2
VSS
MA1
MA2
MA0
MA4
MA3
VSS
MA5
VSS
MA8
MA6
MA10
PCLK
FLT#
VDAT5
VSS
VCC2
MD31
VSS
MD60
MD57
VSS
MD22
MD52
VSS
VCC2
VCC2
VSS
BA1
MA9
MA7
VRDY
VSS
VDAT0
SDCLK0
SDCLK2
SDCLKIN
MD29
MD27
MD56
MD55
MD21
MD20
MD50
MD16
DQM3
CS3#
VSS
BA0
VCC2
VDAT4
VDAT2
SDCLK1
VCC2
RWCLK
SDCLKOUT
VSS
MD58
VCC3
MD23
VSS
MD19
MD49
VCC2
DQM6
CKEA
MA11
VCC3
VDAT7
VDAT3
ENDIS
SDCLK3
MD63
MD30
MD61
MD59
MD25
MD24
MD53
MD51
MD18
MD48
DQM7
DQM2
MA12
NC
VSS
VCC2
VDAT1
VSS
VCC2
MD62
VCC3
MD28
MD26
VSS
MD54
CKEB
VCC3
MD17
VCC2
VSS
CS1#
VCC3
VSS
Note:
Signal names have been abbreviated in this figure due to space constraints.
= Denotes GND terminal
= Denotes PWR terminal (VCC2 = VCC_CORE; VCC3 = VCC_IO)
320 SPGA - Top View
GXLV
Processor
Geode