參數(shù)資料
型號： 28F640J3C-120
廠商： Intel Corp.
英文描述： Intel StrataFlash Memory (J3)
中文描述： 英特爾StrataFlash存儲器（J3）
文件頁數(shù)： 23/72頁
文件大?。?/td> 905K
代理商： 28F640J3C-120
256-Mbit J3 (x8/x16)
Datasheet
23
R12
t
FLQV/
t
FHQV
BYTE# to Output Delay
1000
1000
1000
1000
1000
1,2
R13
t
FLQZ
BYTE# to Output in High Z
1000
1000
1000
1000
1000
1,2,5
R14
t
EHEL
CEx High to CEx Low
0
0
0
0
0
1,2,5
R15
t
APA
Page Address Access Time
25
25
25
30
25
5, 6
R16
t
GLQV
OE# to Array Output Delay
25
25
25
25
25
4
NOTES:
CE
X
low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CE
X
high is
defined at the first edge of CE0, CE1, or CE2 that disables the device (see
Table 13
).
1. See AC Input/Output Reference Waveforms for the maximum allowable input slew
rate.
2. OE# may be delayed up to t
-t
after the first edge of CE0, CE1, or CE2 that
enables the device (see
Table 13
) without impact on t
.
3. See
Figure 15, “Transient Input/Output Reference Waveform for VCCQ = 2.7 V–3.6
V” on page 29
and
Figure 16, “Transient Equivalent Testing Load Circuit” on
page 30
for testing characteristics.
4. When reading the flash array a faster t
(R16) applies. Non-array reads refer to
Status Register reads, query reads, or device identifier reads.
5. Sampled, not 100% tested.
6. For devices configured to standard word/byte read mode, R15 (t
APA
) will equal R2
(t
AVQV
).
Figure 9. Single Word Asynchronous Read Waveform
Table 8. Read Operations (Sheet 2 of 2)
Asynchronous
Specifications
(All units in ns unless
otherwise noted)
V
CC
= 2.7 V–3.6 V
(3)
V
CCQ
= 2.7 V–3.6 V
(3)
Notes
Speed
Bin
-110
-115
-120
-125
-150
#
Sym
Parameter
Density
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
R11
R5
R12
R13
R10
R4
R16
R7
R6
R9
R8
R3
R1
R2
Address [A]
CEx [E]
OE# [G]
WE# [W]
Data [D/Q]
BYTE#[F]
RP# [P]
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