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參數(shù)資料
| 型號： | 28F016SC |
| 英文描述： | Evaluation Kit/Evaluation System for the MAX5954L/MAX5954A |
| 中文描述： | 28F016SC -字節(jié)寬SmartVoltage FlashFile Memory系列4。 8。及16兆比特 |
| 文件頁數(shù)： | 24/59頁 |
| 文件大?。?/td> | 384K |
| 代理商： | 28F016SC |
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3 VOLT ADVANCED+ BOOT BLOCK
E
24
PRODUCT PREVIEW
substantially reduces power consumption. Outputs
are placed in a high-mpedance state independent
of the status of the OE# signal. If CE# transitions to
a logic-high level during erase or program
operations, the device will continue to perform the
operation and consume corresponding active power
until the operation is completed.
System engineers should analyze the breakdown of
standby time versus active time and quantify the
respective power consumption in each mode for
their specific application. This will provide a more
accurate measure of application-specific power and
energy requirements.
3.6.4
DEEP POWER-DOWN MODE
The deep power-down mode is activated when
RP#
=
V
IL
(GND
±
0.2 V). During read modes, RP#
going low de-selects the memory and places the
outputs in a high impedance state. Recovery from
deep power-down requires a minimum time of t
PHQV
for read operations and t
PHWL
/t
PHEL
for write
operations.
During program or erase modes, RP# transitioning
low will abort the in-progress operation. The
memory contents of the address being programmed
or the block being erased are no longer valid as the
data integrity has been compromised by the abort.
During deep power-down, all internal circuits are
switched to a low power savings mode (RP#
transitioning to V
IL
or turning off power to the device
clears the status register).
3.7
Power-Up/Down Operation
The device is protected against accidental block
erasure or programming during power transitions.
Power supply sequencing is not required, since
the
device is indifferent as to which power supply, V
PP
or V
CC
, powers-up first.
3.7.1
RP# CONNECTED TO SYSTEM
RESET
The use of RP# during system reset is important
with automated program/erase devices since the
system expects to read from the flash memory
when it comes out of reset. If a CPU reset occurs
without a flash memory reset, proper CPU
initialization will not occur because the flash
memory may be providing status information
instead of array data. Intel recommends connecting
RP# to the system CPU RESET# signal to allow
proper CPU/flash initialization following system
reset.
System designers must guard against spurious
writes when V
CC
voltages are above V
LKO
. Since
both WE# and CE# must be low for a command
write, driving either signal to V
IH
will
inhibit writes to
the device. The CUI architecture provides additional
protection since alteration of memory contents can
only occur after successful completion of the two-
step command sequences. The device is also
disabled until RP# is brought to V
IH
, regardless of
the state of its control inputs. By holding the device
in reset (RP# connected to system PowerGood)
during power-up/down, invalid bus conditions during
power-up can be masked, providing yet another
level of memory protection.
3.7.2
V
CC
, V
PP
AND RP# TRANSITIONS
The CUI latches commands as issued by
system
software and is not altered by V
PP
or CE#
transitions or WSM actions. Its default state upon
power-up, after exit from reset mode or after V
CC
transitions above V
LKO
(Lockout voltage), is read
array mode.
After any program or block erase operation is
complete (even after V
PP
transitions down to
V
PPLK
), the CUI must be reset to read array mode
via the Read Array command if access to the flash
memory array is desired.
3.8
Power Supply Decoupling
Flash memory’s power switching characteristics
require
careful
device
designers should consider three supply current
issues:
1.
Standby current levels (I
CCS
)
2.
Read current levels (I
CCR
)
3.
Transient peaks produced by falling and rising
edges of CE#.
decoupling.
System
Transient current magnitudes depend on the device
outputs’ capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection
will suppress these transient voltage peaks. Each
flash device should have a 0.1 μF ceramic
capacitor connected between each V
CC
and GND,
and between its V
PP
and GND. These high-
frequency, inherently low-inductance capacitors
should be placed as close as possible to the
package leads.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 28F032C3 | 3 VOLT ADVANCED+ BOOT BLOCK. 8-. 16-. 32-MBIT FLASH MEMORY FAMILY |
| 28F160F3 | 5V/3.3V or Adjustable, Low-Dropout, Low-IQ, 500mA Linear Regulators |
| 28F800F3 | 3 Volt Fast Boot Block Flash Memory(3 V 8M位快速引導(dǎo)塊閃速存儲器) |
| 28F160F3 | 16MBIT Fast Boot Block Flash Memory(16兆位的快速引導(dǎo)塊閃速存儲器) |
| 28F2001BX-T | 5V/3.3V or Adjustable, Low-Dropout, Low-IQ, 500mA Linear Regulators |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28F016SV | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:16-MBIT (1 MBIT x 16, 2 MBIT x 8) FlashFile MEMORY |
| 28F016XD | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:16-MBIT (1 MBIT x 16) DRAM-INTERFACE FLASH MEMORY |
| 28F016XS | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:16-MBIT (1 MBIT x 16, 2 MBIT x 8) SYNCHRONOUS FLASH MEMORY |
| 28F0181-1SR-10 | 功能描述:電磁干擾濾波珠子、扼流圈和陣列 115ohms 100MHz 10A Broad Band Frequency RoHS:否 制造商:AVX 阻抗: 最大直流電流:35 mA 最大直流電阻: 容差: 端接類型:SMD/SMT 電壓額定值:25 V 工作溫度范圍:- 25 C to + 85 C 封裝 / 箱體:0603 (1608 metric) |
| 28F020 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:28F020 2048K (256K X 8) CMOS FLASH MEMORY |
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