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參數(shù)資料
| 型號(hào)： | 0W633-001-XTP |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | BelaSigna 250 - 16 bit Audio Processor, Full Stereo 2-in, 2-out; Package: LFBGA 57, 5x5; No of Pins: 57; Container: Tape and Reel; Qty per Container: 5000 |
| 中文描述： | 0-BIT, 50 MHz, MIXED DSP, PBGA49 |
| 封裝： | 5 X 5 MM, GREEN, CABGA-49 |
| 文件頁數(shù)： | 4/34頁 |
| 文件大?。?/td> | 935K |
| 代理商： | 0W633-001-XTP |
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Rev. 7 | Page 12 of 34 | www.onsemi.com
BelaSigna 250
The multiplier takes 16-bit values and performs a multiplication every time an operand is loaded into either the X or Y registers.
A number of instructions that allow loading of X and Y simultaneously and addition of the new product to the previous product
(a MAC operation) are available. Single-cycle MAC with data pointer update and fetch is supported.
The arithmetic logic unit (ALU) receives its input from either the accumulator (AE|AH|AL) or the product register (PH|PL).
Although the RCore is a 16-bit system, 32-bit additions or subtractions are also supported. Bit manipulation is also available on
the accumulator, as are operations to perform arithmetic or logic shifting, toggling of specific bits, limiting, and other functions.
2. Data Movement Instructions
Data movement instructions transfer data between RAM, control registers and the RCore’s internal registers (accumulator, PH,
PL, etc.).
Two address generators are available to simultaneously generate two addresses in a single cycle. The address pointers R0..2
and R4..6 can be configured to support increment, decrement, add-by-offset, and two types of modulo-N circular buffer
operations. Single-cycle access to low-X memory or low-Y memory as well as two-cycle instructions for immediate access to
any address, are also available.
3. Program Flow Control Instructions
The RCore supports repeating of both single-word instructions and larger segments of code using dedicated repeat
instructions or hardware loop counters. Furthermore, instructions to manipulate the program counter (PC) register such as
calls to subroutines, conditional branches and unconditional branches are also provided.
The full instruction set may be seen in Table 6.
Table 6: Instruction Set
Instruction
Description
Instruction
Description
ABS A [,Cond] [,DW]
Calculate absolute value of A on condition
DCMP
Compare PH | PL to A
ADD A, Reg [,C]
Add register to A
DEC A [,Cond] [,DW]
Decrement A on condition
ADD A, (Rij) [,C]
Add memory to A
DEC Reg [Cond]
Decrement register on condition
ADD A, DRAM [,B]
Add (DRAM) to A
DEC (Rij) [,Cond]
Decrement memory on condition
ADD A, (Rij)p [,C]
Add program memory to A
DSUB [Cond] [,P]
Subtract PH | PL from A, update
PH | PL on condition
ADD A, Rc [,C]
Add Rc register to A
EOR A, Reg
Exclusive-OR register with AH to AH
ADDI A, IMM [,C]
Add IMM to A
EOR A, (Rij)
Exclusive-OR memory with AH to AH
ADSI A, SIMM
Add signed SIMM to A
EOR A, DRAM [,B]
Exclusive-OR (DRAM) with AH to AH
AND A, Reg
AND register with AH to AH
EOR A, (Rij)p
Exclusive-OR program memory with AH to AH
AND A, (Rij)
AND memory with AH to AH
EOR A, Rc
Exclusive-OR Rc register with AH to AH
AND A, DRAM [,B]
AND (DRAM) with AH to AH
EORI A, IMM
Exclusive-OR IMM with AH to AH
AND A, (Rij)p
AND program memory with AH to AH
EOSI A, SIMM
Exclusive-OR unsigned SIMM with AH to AH
AND A, Rc
AND Rc register with AH to AH
INC A [,Cond] [,DW]
Increment A on condition
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