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參數(shù)資料
| 型號(hào)： | 0W633-001-XTP |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | BelaSigna 250 - 16 bit Audio Processor, Full Stereo 2-in, 2-out; Package: LFBGA 57, 5x5; No of Pins: 57; Container: Tape and Reel; Qty per Container: 5000 |
| 中文描述： | 0-BIT, 50 MHz, MIXED DSP, PBGA49 |
| 封裝： | 5 X 5 MM, GREEN, CABGA-49 |
| 文件頁(yè)數(shù)： | 3/34頁(yè) |
| 文件大?。?/td> | 935K |
| 代理商： | 0W633-001-XTP |
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Rev. 7 | Page 11 of 34 | www.onsemi.com
BelaSigna 250
the system are accessible by the RCore using several addressing modes including indirect and circular modes. The RCore assumes
master functionality of the system.
3.1.1. RCore DSP Architecture
Figure 6 illustrates the architecture of the RCore.
Figure 6: RCore DSP Architecture
The RCore is a single-cycle pipelined multiply-accumulate (MAC) architecture that feeds into a 40-bit accumulator complete with barrel
shifter for fast normalization and de-normalization operations. Program execution is controlled by a sequencer that employs a three-
stage pipeline (FETCH, DECODE, EXECUTE). Furthermore, the RCore incorporates pointer configuration registers for low cycle-count
address generation when accessing the three memories: program memory (PRAM), X data memory (XRAM) and Y data memory
(YRAM).
3.1.2. Instruction Set
The RCore instruction set can be divided into the following three classes:
1. Arithmetic and Logic Instructions
The RCore uses two's-complement fractional as a native data format. Thus, the range of valid numbers is [-1; 1), which is
represented by 0x8000 to 0x7FFF. Other formats can be utilized by applying appropriate shifts to the data.
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