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參數(shù)資料
| 型號： | 0W633-001-XTP |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | BelaSigna 250 - 16 bit Audio Processor, Full Stereo 2-in, 2-out; Package: LFBGA 57, 5x5; No of Pins: 57; Container: Tape and Reel; Qty per Container: 5000 |
| 中文描述： | 0-BIT, 50 MHz, MIXED DSP, PBGA49 |
| 封裝： | 5 X 5 MM, GREEN, CABGA-49 |
| 文件頁數(shù)： | 34/34頁 |
| 文件大小： | 935K |
| 代理商： | 0W633-001-XTP |
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Rev. 7 | Page 9 of 34 | www.onsemi.com
BelaSigna 250
2.1.5. Internal Power Supplies
Power management circuitry in BelaSigna 250 generates separate digital (VDDC) and analog (VREG, VDBL) regulated supplies. Each
supply requires an external decoupling capacitor, even if the supply is not used externally. Decoupling capacitors should be placed as
close as possible to the power pads. Further details on these critical signals are provided in Table 4. Non-critical signals are outlined in
Table 5.
Table 4: Critical Signals
Pin Name
Description
Routing Guideline
VBAT
Power supply
Place 1μF (min) decoupling capacitor close to pin. Connect negative
terminal of capacitor to DGND plane.
VREG, VDBL
Internal regulator for analog
sections
Place separate 1μF decoupling capacitors close to each pin. Connect
negative capacitor terminal to AGND. Keep away from digital traces and
output traces. VREG may be used to generate microphone bias. VDBL
shall not be used to supply external circuitry.
AGND
Analog ground return
Connect to AGND plane.
VDDO / VDDC
Internal regulator for digital
sections (pads and core)
Place 10μF decoupling capacitor close to pin. Connect negative terminal
of capacitor to DGND (Unique pin on the WLCSP option).
GNDO / GNDC
Digital ground return (pads and
core)
Connect to digital ground.
AI0, AI1 / LOUT, AI2, AI3
Microphone inputs
Keep as short as possible. Keep away from all digital traces and audio
outputs. Avoid routing in parallel with other traces. Connect unused
inputs to AGND.
AIR
Input stage reference voltage
Connect to AGND. If no analog ground plane, should share trace with
microphone grounds to star point.
AO0, AO1
Analog audio output
Keep away from microphone inputs.
RCVR0+, RCVR0-, RCVR1+,
RCVR1-
Direct digital audio output
Keep away from analog traces, particularly microphone inputs. Route
corresponding traces as differential pair; route parallel to each other and
approximately the same length.
AOR
Output stage reference voltage
Connect to star point. Share trace with power amplifier (if present).
RCVRGND
Output stage ground return
Connect to star point. Keep away from analog inputs.
EXT_CLK
External clock input / internal
clock output
Minimize trace length. Keep away from analog signals. If possible,
surround with digital ground.
AI_RC
Infrared receiver input
If used, minimize trace length to photodiode.
Not available on the WLCSP option
Table 5: Non-Critical Signals
Pin Name
Description
Routing Guideline
CAP0, CAP1
Internal charge pump - capacitor connection
Place 100nF capacitor close to pins
DEBUG_TX, DEBUG_RX
Debug port
Not critical
Connect to test points
TWSS_SDA, TWSS_CLK
TWSS port
Not critical
GPIO[14..0]
General-purpose I/O
Not critical
GPIO[15]
General-purpose I/O
Determines voltage mode during boot. For 1.8V operation,
should be connected to DGND.
Not critical
UART_RX, UART_TX
General-purpose UART
Not critical
PCM_FRAME, PCM_CLK, PCM_OUT,
PCM_IN
Pulse code modulation port
Not critical Keep away from analog
signals.
I2S_INA, I2S_IND, I2S_FA, I2S_FD,
I2S_OUTA, I2S_OUTD
Philips IS compatible port
Not critical
UCLK
Programmable clock output
Not critical
If used, keep away from analog
inputs/outputs
LSAD[5..0]
Low-speed A/D converters
Not critical
SPI_CLK, SPI_CS, SPI_SERI,
SPI_SERO
Serial peripheral interface port
Connect to EEPROM
Not critical
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