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參數(shù)資料
| 型號： | μPDPD30101 |
| 廠商： | NEC Corp. |
| 英文描述： | 64-Bit Micro[rocessor(64位微處理器) |
| 中文描述： | 64位微[rocessor（64位微處理器） |
| 文件頁數(shù)： | 9/97頁 |
| 文件大?。?/td> | 409K |
| 代理商： | ΜPDPD30101 |
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μ
PD30101
8
1. PIN FUNCTIONS
1.1 Pin Functions
(1) System bus interface signals
Signal Name
I/O
Functional Description
ADD (0:20)
Output
21-bit address bus. Used to specify addresses of DRAM, ROM, LCD, or PCMCIA.
DATA (0:15)
I/O
16-bit data bus. Used to transfer data from V
R
4101 to DRAM, ROM, LCD, or PCMCIA,
and vice versa.
LCDCS
Output
LCD chip select signal. Asserted active when V
R
4101 accesses LCD via ADD bus and
DATA bus.
LCDOE
Output
LCD output enable signal. Asserted active when V
R
4101 reads data from LCD.
LCDWE/ROMWE
Output
Multiplexed signal of LCD write enable signal and flash memory write enable signal.
This signal functions as LCD write enable signal when LCDCS pin is active, and is
asserted active when V
R
4101 writes data to LCD. When LCDCS pin is inactive, this
signal functions as ROM write enable signal, and is asserted active when V
R
4101
writes data to flash memory.
LCDRDY
Input
LCD ready signal. Assert this signal active when LCD or PCMCIA controller is ready
for access by V
R
4101.
ROMCS (0:3)
Output
ROM chip select signals. Used to select ROM to be accessed from up to four ROMs
connected to V
R
4101.
ROMOE
Output
ROM output enable signal. Asserted active when V
R
4101 reads data from ROM.
MRAS (0:3)
Output
RAS signals of DRAM. Asserted active when valid row address of RAM to be accessed
is output onto ADD bus. Up to four RAMs can be connected to V
R
4101.
UCAS
Output
CAS signal of DRAM. Asserted active when valid column address is output onto ADD
bus when high-order byte of DRAM is accessed.
LCAS
Output
CAS signal of DRAM. Asserted active when valid column address is output onto ADD
bus when low-order byte of DRAM is accessed.
RAMWE
Output
DRAM write enable signal. Asserted active when V
R
4101 writes data to DRAM.
PCMCLK
Output
PCMCIA card clock. Outputs 8-MHz clock to be supplied to PCMCIA controller.
SHB
Output
PCMCIA bus high byte enable signal. Asserted active if high-order byte of DATA bus
is valid when PCMCIA is accessed.
IOR
Output
PCMCIA card I/O read signal. Asserted active when V
R
4101 reads data from I/O port
of PCMCIA.
IOW
Output
PCMCIA card I/O write signal. Asserted active when V
R
4101 writes data to I/O of
PCMCIA.
MEMR
Output
PCMCIA card memory read signal. Asserted active when V
R
4101 reads data from
memory of PCMCIA.
MEMW
Output
PCMCIA card memory write signal. Asserted active when V
R
4101 writes data to
memory of PCMCIA.
ZWS
Input
PCMCIA zero wait state signal. Assert this signal active when PCMCIA controller is
ready for access by V
R
4101.
IRQ
Input
PCMCIA card interrupt request signal. PCMCIA controller asserts this pin active to
inform V
R
4101 of interrupt.
RSTOUT
Output
PCMCIA card reset signal. Asserted active when V
R
4101 resets PCMCIA controller.
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