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參數資料
| 型號： | μPDPD30101 |
| 廠商： | NEC Corp. |
| 英文描述： | 64-Bit Micro[rocessor(64位微處理器) |
| 中文描述： | 64位微[rocessor（64位微處理器） |
| 文件頁數： | 20/97頁 |
| 文件大?。?/td> | 409K |
| 代理商： | ΜPDPD30101 |
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μ
PD30101
19
(b) DMADD16 (Doubleword Multiply and Add 16-bit register)
This instruction multiplies the contents of general-purpose register rs by the contents of general-purpose
register rt. Both the operands are treated as signed 16-bit integers. Bits 62 through 15 of both the
operands must be sign-extended.
The result of the multiplication is added to the value of special register LO. The result of the addition
is treated as a signed integer. The 64-bit result is loaded to special register LO.
An integer overflow exception does not occur.
This operation is defined in the 64-bit mode and 32-bit kernel mode. If this instruction is encountered
in the 32-bit user/supervisor mode, a reserved instruction exception occurs.
(4) Addition of power mode instructions
The V
R
4101 supports three power modes to lower the power consumption, and therefore, has dedicated
instructions that set these modes. Note that the power mode instructions are not correctly executed by any
other processors in the V
R
series.
The operations of the power mode instructions are as follows:
(a) STANDBY
This instruction places the processor in the Standby mode from the Fullspeed mode.
When instruction execution has proceeded to the WB stage, and the SysAD bus has entered the idle
status, the internal clock is fixed to the high level, and the pipeline operation is stopped.
In the Standby mode, the PLL, clocks related to timers/interrupts, and interface clocks to the peripheral
function blocks (TClock and MasterOut) operate normally.
When the processor is in the Standby mode it is returned to the Fullspeed mode by any interrupt including
an internally generated timer interrupt.
(b) SUSPEND
This instruction places the processor in the Suspend mode from the Fullspeed mode.
When instruction execution has proceeded to the WB stage, and the SysAD bus has entered the idle
status, the internal clock and TClock are fixed to the high level, and the pipeline operation and interfacing
to the peripheral function blocks are stopped.
In the Suspend mode, the PLL, clocks related to timers/interrupts, and MasterOut operate normally.
The processor remains in the Suspend mode until it accepts an interrupt. When the processor accepts
an interrupt, it returns to the Fullspeed mode.
(c) HIBERNATE
This instruction places the processor in the Hibernate mode from the Fullspeed mode.
When instruction execution has proceeded to the WB stage, and the SysAD bus has entered the idle
status, all the clocks are fixed to the high level, and the pipeline operation is stopped.
The processor remains in the Hibernate mode until either the POWER pin is asserted active or the
WakeUp timer interrupt occurs. The processor returns to the Fullspeed mode when the POWER pin
is asserted active, when the WakeUp Timer interrupt occurs, or when the DCD pin is asserted active.
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