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參數(shù)資料
| 型號： | μPDPD30101 |
| 廠商： | NEC Corp. |
| 英文描述： | 64-Bit Micro[rocessor(64位微處理器) |
| 中文描述： | 64位微[rocessor（64位微處理器） |
| 文件頁數(shù)： | 24/97頁 |
| 文件大?。?/td> | 409K |
| 代理商： | ΜPDPD30101 |
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μ
PD30101
23
Figure 3-6. Byte Address in Double Word: Little Endian
High-order
address
Low-order
address
Double word
address
16
8
0
63
32 31
0
Word
Half word
Byte
23
22
15
7
14
6
21
13
5
20
12
4
19
11
3
18
10
2
17
9
1
16
8
0
16 15
8 7
Remarks 1.
The least significant byte is the lowest address.
2.
A word is addressed by the address of the least significant byte.
3.6 Virtual Storage
The V
R
4101 has a virtual storage management mechanism using TLB.
Virtual addresses are used for address management by software or address calculation of the pipeline. To access
memories for program fetch and data access, and internal I/O and external I/O, physical addresses translated by TLB
are used.
Note that part of the virtual address space is not translated by TLB, but is translated to physical addresses by merely
changing specific addresses. If only this part of the address space is used, the V
R
4101 can be treated in the same
manner as a CPU that operates with physical addresses.
3.6.1 Virtual address space
The V
R
4101 has two operation modes, 32-bit mode and 64-bit mode, and three types of operating modes: user mode,
supervisor mode, and kernel mode. The virtual address space in each mode is shown below.
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