參數(shù)資料
型號: μPD9210FGC-7EA
廠商: NEC Corp.
英文描述: USB Host Controller(USB主控制器)
中文描述: USB主機控制器(的USB主控制器)
文件頁數(shù): 61/95頁
文件大小: 423K
代理商: ΜPD9210FGC-7EA
CHAPTER 5 REGISTER INFORMATION
61
Table 5-4. Status Register Information
Field
bit
Read/
Write
Value
Comment
Reserved
4 : 0
R
00000b
Reserved
66MHz capable
5
R
0b
33-MHz operation
UDF supported
6
R
0b
UDF is not supported.
Fast back-to-back capable
7
R
0b
Fast back-to-back access is not supported.
Data Parity Error detected
8
R/W
“1” is set to this bit when the following three conditions are
met.
(1) Either PERR# was asserted by the parity error source or
assertion of PERR# by the target source was detected.
(2) The parity error source was the bus master during the bus
cycle in which the data parity error occurred.
(3) “1” has been set to the command register’s Parity Error
response bit.
DEVSEL timing
10 : 9
R
01b
DEVSEL# assert timing: Medium speed
Signaled target abort
11
R/W
The target sets “1” if the bus cycle it is accessing ends due to
a target abort condition.
Received target abort
12
R/W
The master sets “1” if the bus cycle it is executing ends due to
a target abort condition.
Received master abort
13
R/W
The master sets “1” if the bus cycle it is executing ends due to
a master abort condition.
Signaled system error
14
R/W
“1” is set to this bit when SERR# is asserted.
Detected parity error
15
R/W
“1” is set to this bit when data parity or address parity is
detected.
Table 5-5. Base Address (BAR_OHCI) Register Information
Field
bit
Read/
Write
Value
(Default)
Comment
Memory space indicator
0
R
0b
Operational registers are mapped to main memory
space.
Type
2 : 1
R
00b
Operational registers can be allocated in any part
of the 4-G main memory space.
Prefetchable
3
R
0b
Prefetch is disabled.
Base address (LSB)
11 : 4
R
00h
Operational registers have a 4-Kbyte address
space.
Base address (MSB)
31 : 12
R/W
000h
Indicates the high-order 20 bits of the base
address in the Operational registers.
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