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| 型號(hào)： | μPD70F3003 |
| 廠商： | NEC Corp. |
| 英文描述： | 16/32 Bit Single Chip Microcontrollers(16/32 位單片微控制器) |
| 中文描述： | 16/32位單片機(jī)微控制器（16/32位單片微控制器） |
| 文件頁(yè)數(shù)： | 130/141頁(yè) |
| 文件大?。?/td> | 374K |
| 代理商： | ΜPD70F3003 |
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APPENDIX A INSTRUCTION MNEMONIC (IN ALPHABETICAL ORDER)
118
Table A-1. Instruction Mnemonic (in alphabetical order) (3/7)
Instruction
Mnemonic
Operand
Format
CY
OV
S
Z
SAT
Instruction Function
LDSR
reg2, regID
IX
–
–
–
–
–
Load to system register. Set the word data of
reg2 to a system register specified by regID. If
regID is PSW, the values of the corresponding
bits of reg2 are set to the respective flags of the
PSW.
MOV
reg1, reg2
I
–
–
–
–
–
Moves data. Transfers the word data of reg1 to
reg2.
MOV
imm5, reg2
II
–
–
–
–
–
Moves data. Transfers the value of a 5-bit
immediate data,sign-extended to word length, to
reg2.
MOVEA
imm16, reg1, reg2
VI
–
–
–
–
–
Moves effective address. Adds a 16-bit immediate
data, sign-extended to word length, to the word
data of reg1, and stores the result to reg2.
MOVHI
imm16, reg1, reg2
VI
–
–
–
–
–
Moves higher half-word. Adds word data, in
which the higher 16 bits are defined by the 16-bit
immediate data while the lower 16 bits are set to
0, to the word data of reg1 and stores the result
to reg2.
MULH
reg1, reg2
I
–
–
–
–
–
Signed multiply. Multiplies the lower half-word
data of reg2 by the lower half-word data of reg1,
and stores the result to reg2 as word data.
MULH
imm5, reg2
II
–
–
–
–
–
Signed multiply. Multiplies the lower half-word
data of reg2 by a 5-bit immediate data, sign-
extended to half-word length, and stores the
result to reg2 as word data.
MULHI
imm16, reg1, reg2
VI
–
–
–
–
–
Signed multiply. Multiplies the lower half-word
data of reg1 by a 16-bit immediate data, and
stores the result to reg2.
NOP
–
I
–
–
–
–
–
No operation. Executes nothing and consumes
at least one clock cycle.
NOT
reg1, reg2
I
–
0
*
*
–
Logical Not. Logically negates (takes 1’s comple-
ment of) the word data of reg1, and stores the
result to reg2.
NOT1
bit#3, disp16 [reg1]
VIII
–
–
–
*
–
Bit not. First, adds the data of reg1 to a 16-bit
displacement, sign-extended to word length, to
generate a 32-bit address. The bit specified by
the 3-bit field “bbb” is inverted at the byte data
location referenced by the generated address.
OR
reg1, reg2
I
–
0
*
*
–
Logical sum. ORs the word data of reg2 with the
word data of reg1, and stores the result to reg2.
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