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| 型號(hào)： | μPD70F3003 |
| 廠商： | NEC Corp. |
| 英文描述： | 16/32 Bit Single Chip Microcontrollers(16/32 位單片微控制器) |
| 中文描述： | 16/32位單片機(jī)微控制器（16/32位單片微控制器） |
| 文件頁(yè)數(shù)： | 123/141頁(yè) |
| 文件大?。?/td> | 374K |
| 代理商： | ΜPD70F3003 |
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111
CHAPTER 8 PIPELINE
8.3.2 Referencing execution result of load instruction
For load instructions (LD, SLD), data read in the MEM stage is saved during the WB stage. Therefore, if the contents
of the same register are used by the instruction immediately after the load instruction, it is necessary to delay the
use of the register by this later instruction until the load instruction has ended using that register. This is called a hazard.
The V850 family has an interlock function that causes the CPU to automatically handle this hazard by delaying the
ID stage of the next instruction.
The V850 family also has a short path that allows the data read during the MEM stage to be used in the ID stage
of the next instruction. This short path allows data to be read with the load instruction during the MEM stage and the
use of this data in the ID stage of the next instruction with the same timing.
As a result of the above, when using the execution result in the instruction following immediately after, the number
of execution clocks of the load instruction is 2.
Figure 8-4. Example of Execution Result of Load Instruction
IL :
– :
Idle inserted for data wait by interlock function
Idle inserted for wait
Short path
:
As described above, when an instruction placed immediately after a load instruction uses its execution result, a
data wait time occurs due to the interlock function, and the execution speed is lowered. This drop in execution speed
can be avoided by placing instructions that use the execution result of a load instruction at least 2 instructions after
the load instruction.
8.3.3 Referencing execution result of multiply instruction
For multiply instructions (MULH, MULHI), the operation result is saved to the register in the WB stage. Therefore,
if the contents of the same register are used by the instruction immediately after the multiply instruction, it is necessary
to delay the use of the register by this later instruction until the multiply instruction has ended using that register
(occurrence of hazard).
The V850 family’s interlock function delays the ID stage of the instruction following immediately after. A short path
is also provided that allows the EX2 stage of the multiply instruction and the multiply instruction’s operation result
to be used in the ID stage of the instruction following immediately after with the same timing.
Figure 8-5. Example of Execution Result of Multiply Instruction
IL :
– :
Idle inserted for data wait by interlock function
Idle inserted for wait
Short path
:
IF
ID
IF
EX
IL
IF
MEM
ID
–
WB
EX
ID
IF
MEM
EX
ID
Load instruction 1
(LD [R4], R6)
Instruction 2 (ADD 2, R6)
Instruction 3
Instruction 4
WB
MEM
EX
MEM
WB
WB
1
2
3
4
5
6
7
8
9
IF
ID
IF
EX1
IL
IF
EX2
ID
–
WB
EX
ID
IF
MEM
EX
ID
Instruction 2 (ADD 2, R6)
Instruction 3
Instruction 4
WB
MEM
EX
MEM
WB
WB
1
2
3
4
5
6
Multiply instruction 1
(MULH 3, R6)
7
8
9
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