參數(shù)資料
型號： μPD70F3003
廠商： NEC Corp.
英文描述： 16/32 Bit Single Chip Microcontrollers(16/32 位單片微控制器)
中文描述： 16/32位單片機微控制器（16/32位單片微控制器）
文件頁數(shù)： 106/141頁
文件大?。?/td> 374K
代理商： ΜPD70F3003
CHAPTER 6 INTERRUPT AND EXCEPTION
94
Table 6-1. Interrupt/Exception Codes
Interrupt/Exception Cause
Classification
Exception Code
Handler Address
Return PC
Name
Trigger
NMI
NMI input
Interrupt
0010H
00000010H
next PC
Note
2
Maskable interrupt
Note 1
Interrupt
Note 1
Note 1
next PC
Note
2
TRAP0n (n = 0 - FH)
TRAP instruction
Exception
004nH
00000040H
next PC
TRAP1n (n = 0 - FH)
TRAP instruction
Exception
005nH
00000050H
next PC
ILGOP
Illegal op code
Exception
006nH
00000060H
next PC
Note
3
Notes 1.
Differs depending on the type of the maskable interrupts.
2.
If an interrupt is acknowledged during execution of a DIVH (divide) instruction, the Restore PC becomes
the PC value for the currently executed instruction (DIVH).
3.
The execution address of the illegal instruction is obtained by “retention PC-4” when an illegal op code
exception occurs.
The return PC is the PC saved to the EIPC or FEPC when interrupt/exception processing is started. “next PC”
is the PC that starts processing after interrupt/exception processing.
The processing of maskable interrupts is controlled by the user through the INTC unit (interrupt controller). The
INTC is different for each device in the V850 family due to the variations of on-chip peripherals, interrupt/exception
causes and exception codes.
6.1 Interrupt Servicing
6.1.1 Maskable interrupt
The maskable interrupt can be masked by the program status word (PSW).
The INTC issues an interrupt request to the CPU, based on the accepted interrupt with the highest priority.
If a maskable interrupt occurs due to INT input, the processor performs the following steps, and transfers control
to the handler routine.
(1) Saves restore PC to EIPC.
(2) Saves current PSW to EIPSW.
(3) Writes exception code to lower half-word of ECR (EICC).
(4) Sets ID bit of PSW and clears EP bit.
(5) Sets handler address for each interrupt to PC and transfers control.
Interrupts are held pending in the interrupt controller (INTC) when one of the following two conditions occur: when
the interrupt input (INT) is masked by its INTC, or when an interrupt service routine is currently being executed (when
the NP bit of the PSW is 1 or when the ID bit of the PSW is 1). Interrupts are enabled by clearing the mask condition
and by resetting the NP and ID bits of the PSW to 0 with the LDSR and RETI instructions, which will be enabling
servicing of a new or already pending interrupt.
The EIPC and EIPSW are used as the status saving registers. These registers must be saved by program to enable
nesting of interrupts because there is only one set of EIPC and EIPSW is provided. Bits 31 through 24 of the EIPC
and bits 31 through 8 of the EIPSW are fixed to 0.
Figure 6-1 illustrates how the maskable interrupt is serviced.
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