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參數(shù)資料
| 型號(hào)： | μPD70F3003 |
| 廠商： | NEC Corp. |
| 英文描述： | 16/32 Bit Single Chip Microcontrollers(16/32 位單片微控制器) |
| 中文描述： | 16/32位單片機(jī)微控制器（16/32位單片微控制器） |
| 文件頁(yè)數(shù)： | 115/141頁(yè) |
| 文件大?。?/td> | 374K |
| 代理商： | ΜPD70F3003 |
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CHAPTER 8 PIPELINE
The V850 family is based on the RISC architecture and executes almost all the instructions in one clock cycle under
control of a 5-stage pipeline.
The processor uses a 5-stage pipeline.
The operation to be performed in each stage is as follows:
IF (instruction fetch) ............................................................
ID (instruction decode)........................................................
Instruction is fetched and fetch pointer is incremented.
Instruction is decoded, immediate data is generated,
and register is read.
The instruction is executed.
Memory at specified address is accessed.
Result of execution is written to register.
EX (execution of ALU, multiplier, and barrel shifter).........
MEM (memory access) .......................................................
WB (write back) ...................................................................
8.1 Outline of Operation
The instruction execution sequence of the V850 family consists of five stages including fetch and write back stages.
The execution time of each stage differs depending on the type of the instruction and the type of the memory to
be accessed.
As an example of pipeline operation, Figure 8-1 shows the processing of the CPU when nine standard instructions
are executed in succession.
Figure 8-1. Example of Executing Nine Standard Instructions
1 through 13 in the figure above indicate the states of the CPU. In each state, write back of instruction n, memory
access of instruction n+1, execution of instruction n+2, decoding of instruction n+3, and fetching of instruction n+4
are simultaneously performed. It takes five clock cycles to process a standard instruction, including fetching and write
back. Because five instructions can be processed at the same time, however, a standard instruction can be executed
in 1 clock cycle on the average.
IF
ID
IF
EX
ID
IF
MEM WB
EX
ID
IF
MEM WB
EX
ID
IF
MEM WB
EX
ID
IF
MEM WB
EX
ID
IF
MEM WB
EX
ID
IF
MEM WB
EX
ID
IF
MEM WB
EX
ID
MEM WB
EX
MEM WB
1
2
3
4
5
6
7
8
9
10
11
12
13
System Clock
Instruction 1
Instruction 2
Instruction 3
Instruction 4
Instruction 5
Instruction 6
Instruction 7
Instruction 8
Instruction 9
Time Flow (State)
Processing CPU Performs
Simultaneously
End of
Instruc-
tion 3
End of
Instruc-
tion 4
End of
Instruc-
tion 5
End of
Instruc-
tion 6
End of
Instruc-
tion 7
End of
Instruc-
tion 8
End of
Instruc-
tion 9
End of
Instruc-
tion 2
End of
Instruc-
tion 1
Executes Instruction Every 1 Clock Cycle
103
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