
15
LIST OF FIGURES (1/6)
Figure No.
Title
Page
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
CPU Address Space...............................................................................................................................
Image on Address Space.......................................................................................................................
Memory Map...........................................................................................................................................
Internal ROM/Internal Flash Memory Area.............................................................................................
External Memory Area (When Expanded to 64 K, 256 K, or 1 Mbytes) .................................................
External Memory Area (When Expanded to 4 Mbytes) ..........................................................................
Memory Expansion Mode Register (MM) Format...................................................................................
Memory Address Output Mode Register (MAM) Format ........................................................................
Recommended Memory Map (Flash Memory Version)..........................................................................
63
64
66
67
71
72
74
75
78
4-1
Example of Inserting Wait States ...........................................................................................................
94
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5.19
Non-Maskable Interrupt Servicing..........................................................................................................
Acknowledging Non-Maskable Interrupt Request ..................................................................................
RETI Instruction Processing...................................................................................................................
Rising Edge Specification Register (EGP0) Format...............................................................................
Falling Edge Specification Register (EGN0) Format ..............................................................................
Maskable Interrupt Servicing..................................................................................................................
RETI Instruction Processing...................................................................................................................
Example of Interrupt Nesting Service.....................................................................................................
Example of Servicing Interrupt Requests Simultaneously Generated....................................................
Interrupt Control Register (xxICn) Format ..............................................................................................
In-service Priority Register (ISPR) Format .............................................................................................
Watchdog Timer Mode Register (WDTM) Format..................................................................................
Noise Elimination Control Register (NCC)..............................................................................................
Software Exception Processing..............................................................................................................
RETI Instruction Processing...................................................................................................................
Exception Trap Processing ....................................................................................................................
RETI Instruction Processing...................................................................................................................
Pipeline Operation at Interrupt Request Acknowledge...........................................................................
Key Return Mode Register (KRM)..........................................................................................................
111
112
113
115
115
117
118
120
122
123
125
126
127
129
130
132
133
137
138
6-1
6-2
6-3
Format of Processor Clock Control Register (PCC)...............................................................................
Format of Power Saving Control Register (PSC) ...................................................................................
Format of Oscillation Stabilization Time Select Register (OSTS)...........................................................
140
142
143
7-1
7-2
7-3
7-4
Block Diagram of TM0 and TM1.............................................................................................................
16-Bit Timer Mode Control Registers 0, 1 (TMC0, TMC1) .....................................................................
Capture/Compare Control Registers 0, 1 (CRC0, CRC1) ......................................................................
16-Bit Timer Output Control Registers 0, 1 (TOC0, TOC1)....................................................................
154
159
161
163