參數資料
型號: μPD45D128842
廠商: NEC Corp.
英文描述: 128 M-bit Synchronous DRAM with Double Data Rate(128 同步動態(tài)RAM)
中文描述: 128 M位同步雙數據速率(128同步動態(tài)RAM的內存)
文件頁數: 33/80頁
文件大?。?/td> 637K
代理商: ΜPD45D128842
33
μ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
11.4 Read to Write Command Interval
To interrupt the burst read operation using the write command, the burst stop command must be issued to avoid
data conflict. The data bus must be high impedance at least 1 cycle before the write command is issued.
When the write command is issued, any residual data from the burst read cycle must be terminated by the burst stop
command. When /CAS latency is 2, 2.5, the burst stop command must be issued at least 3 cycles prior to the write
command.
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Burst length = 8
T14
T6
T9
Read A
DQS
Command
/CAS latency = 2
/CLK
CKE
T10
T11
Write B
DQ
QA1
QA2
T12
T13
DB1
DB2
Read A
DQS
Command
Write B
DQ
QA1
QA4
/CAS latency = 2.5
DQ and DQS : Output
DQ and DQS : Input
BST
BST
DB1
DB2
QA3
QA4
Hi-Z
Hi-Z
QA2
QA3
DB
DB
T0
T2
T1
T3
T4
T5
Hi-Z
Hi-Z
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