- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄384065 > μPD45D128842 (NEC Corp.) 128 M-bit Synchronous DRAM with Double Data Rate(128 同步動(dòng)態(tài)RAM) PDF資料下載
參數(shù)資料
| 型號(hào)： | μPD45D128842 |
| 廠(chǎng)商： | NEC Corp. |
| 英文描述： | 128 M-bit Synchronous DRAM with Double Data Rate(128 同步動(dòng)態(tài)RAM) |
| 中文描述： | 128 M位同步雙數(shù)據(jù)速率（128同步動(dòng)態(tài)RAM的內(nèi)存） |
| 文件頁(yè)數(shù)： | 22/80頁(yè) |
| 文件大?。?/td> | 637K |
| 代理商： | ΜPD45D128842 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)當(dāng)前第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)
22
μ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
6. Programming the Mode Register
The mode register is programmed by the Mode register set command using address bits BA0, BA1, A11 through A0
as data inputs. The register retains data until it is reprogrammed or the device loses power.
The mode register has four fields ;
Option
/CAS latency
Wrap type
Burst length
: BA0, BA1, A11 through A7
: A6 through A4
: A3
: A2 through A0
Following mode register programming, no command can be issued before at least 2 CLK have elapsed.
/CAS Latency
/CAS latency is the mode critical of the parameters being set. It tells the device how many clocks must elapse
before the data will be available.
The value is determined by the frequency of the clock and the speed grade of the device.
shows the relationship of /CAS latency to the clock period and speed grade of the device.
Burst Length
Burst length is the number of words that will be output or input in a read or write cycle. After a read burst is
completed, the output bus will become Hi-Z.
The burst length is programmable as 2, 4, 8.
Wrap Type (Burst Sequence)
The wrap type specifies the order in which the burst data will be addressed. This order is programmable as either
“Sequential” or “Interleave”. The method chosen will depend on the type of CPU in the system.
Some microprocessor cache system are optimized for sequential addressing and others for interleaved addressing.
7.1 Burst Length and Sequence
shows the addressing sequence for each burst length using them.
Both sequences support bursts of 2, 4 and 8.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| μPD4811650 | 16M Synchronous Graphics Memory (SGRAM)(16M同步圖形存儲(chǔ)器) |
| μPD703002 | 16/32 Bit Single Chip Microcontrollers(16/32 位單片微控制器) |
| μPD703003 | 16/32 Bit Single Chip Microcontrollers(16/32位單片微控制器) |
| μPD703100 | 32 Bit RISC Microcontrollers(32 位 RISC 微控制器) |
| μPD703101 | 32 Bit RISC Microcontrollers(32 位 RISC 微控制器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PD45VN6C100 | 制造商:Banner Engineering 功能描述:SENSOR, PHOTOELECTRIC, PICODOT, CONVERGENT LASER, FOCAL POINT, 1 |
| PD45VN6C100Q | 制造商:Banner Engineering 功能描述:Sensor, PicoDot, Convergent Laser, Focal Point: 102mm, Input 10-30VDC, Cable 2m |
| PD45VN6C200 | 制造商:Banner Engineering 功能描述:PicoDot: Convergent Laser, Focal Point: 203 mm, Input: 10-30V dc, Outputs: Compl |
| PD45VN6C200-52277 | 制造商:Banner Engineering 功能描述:PD45VN6C200-52277 CVGNT LASER 650nm/10nm BANDPASS FILTER |
| PD45VN6C200Q | 制造商:Banner Engineering 功能描述:SENSOR, PHOTOELECTRIC, PICODOT, CONVERGENT LASER, FOCAL POINT |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。