參數(shù)資料
型號(hào): μPD45D128842
廠商: NEC Corp.
英文描述: 128 M-bit Synchronous DRAM with Double Data Rate(128 同步動(dòng)態(tài)RAM)
中文描述: 128 M位同步雙數(shù)據(jù)速率(128同步動(dòng)態(tài)RAM的內(nèi)存)
文件頁數(shù): 41/80頁
文件大?。?/td> 637K
代理商: ΜPD45D128842
41
μ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
13.6.3 Synchronous Characteristics
Parameter
Symbol
-C10
-C12
Unit
MIN.
MAX.
MIN.
MAX.
Frequency
f
CK
CL = 2.5
125
100
MHz
CL = 2
100
83
MHz
Clock cycle time
t
CK
CL = 2.5
8
15
10
15
ns
CL = 2
10
15
12
15
ns
Parameter
Symbol
MIN.
MAX.
Unit
Note
CLK high time
t
CH
0.45
0.55
CLK
CLK low time
t
CL
0.45
0.55
CLK
CLK to /CLK skew
t
cksk
0.015
CLK
Data access time from CLK
t
AC
0.1 x t
CK
0.1 x t
CK
ns
Data Strobe edge to CLK egde skew
t
DQSCK
0.1 x t
CK
0.1 x t
CK
ns
Data Strobe egde to Output Data edge skew
t
DQSQ
0.075 x t
CK
0.075 x t
CK
ns
Output Data valid window
t
DV
0.3 x t
CK
ns
Output Data Strobe valid window
t
DQSV
0.3 x t
CK
ns
DQS entry to Low-Z to first rising edge delay (read)
t
RPRE
0.9 x t
CK
1.1 x t
CK
ns
DQS last falling edge to entry to Hi-z delay (read)
t
RPST
0.4 x t
CK
0.6 x t
CK
ns
Data to Strobe setup time
t
DS
0.075 x t
CK
ns
Data to Strobe hold time
t
DH
0.075 x t
CK
ns
Data mask to Strobe setup time
t
DMS
0.075 x t
CK
ns
Data mask to Strobe hold time
t
DMH
0.075 x t
CK
ns
CLK to DQS write preamble setup time
t
WPRES
0
ns
CLK to DQS write preamble hold time
t
WPREH
0.25 x t
CK
ns
DQS entry to Low-Z to first rising edge delay (write)
t
WPRE
0.4 x t
CK
1.1 x t
CK
ns
DQS last falling edge to entry to Hi-Z delay (write)
t
WPST
0.4 t
CK
0.6 x t
CK
ns
CLK to first rising edge of DQS
t
DQSS
0.75 x t
CK
1.25 x t
CK
ns
Input setup time
t
IS
0.15 x t
CK
ns
Input hold time
t
IH
0.15 x t
CK
ns
Transition time (CLK, /CLK, DQS, DQ, DM)
t
TD
0.5
ns
Transition time (CMD, Add)
t
T
0.5
ns
Remark
If the result of the nominal calculation contains more than one decimal place, the result is rounded up to the
nearest decimal place.
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