參數(shù)資料
型號(hào): μPD45D128842
廠商: NEC Corp.
英文描述: 128 M-bit Synchronous DRAM with Double Data Rate(128 同步動(dòng)態(tài)RAM)
中文描述: 128 M位同步雙數(shù)據(jù)速率(128同步動(dòng)態(tài)RAM的內(nèi)存)
文件頁數(shù): 27/80頁
文件大小: 637K
代理商: ΜPD45D128842
27
μ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
9.2 Write to Precharge Command Interval
In order to write all burst data to the memory cell correctly, the asynchronous parameter t
DPL (MIN.)
must be satisfied.
The t
DPL
specification defines the earliest time that a precharge command can be issued.
CLK
Burst length = 4
T5
Q1
Q2
Q3
WRITE
DQ
Command
Q4
/CAS latency = 2, 2.5
/CLK
DM
(Must satisfy t
RAS
)
PRE
Hi-Z
DQS
Preamble
Postamble
t
DPL
= 1 cycle
T0
T2
T1
T3
T4
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