參數(shù)資料
型號(hào): μPD45D128442
廠商: NEC Corp.
英文描述: 128 M-bit Synchronous DRAM with Double Data Rate(128 同步動(dòng)態(tài)RAM)
中文描述: 128 M位同步雙數(shù)據(jù)速率(128同步動(dòng)態(tài)RAM的內(nèi)存)
文件頁數(shù): 38/80頁
文件大?。?/td> 637K
代理商: ΜPD45D128442
38
μ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
13.4 DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Test condition
Maximum
Unit
Notes
/CAS
latency
Grade
x4
x8
x16
Operating current
I
CC1
t
RC
t
RC(MIN.)
, Io = 0 mA,
CL = 2
-C10
110
120
135
mA
1
-C12
95
100
115
CL = 2.5
-C10
120
130
145
-C12
105
110
125
Precharge standby current
in power down mode
I
CC2P
CKE
V
IL(MAX.)
, t
CK
= 10 ns
25
mA
Precharge standby current
in Non power down mode
I
CC2N
CKE
V
IH(MIN.)
, t
CK
= 10 ns, /CS
V
IH(MIN.)
,
Input signals are changed one time during 20 ns.
40
mA
Active standby current in
power down mode
I
CC3P
CKE
V
IL(MAX.)
, t
CK
= 10 ns
45
mA
Active standby current in
Non power down mode
I
CC3N
CKE
V
IH(MIN.)
, t
CK
= 10 ns, /CS
V
IH(MIN.)
,
Input signals are changed one time during 20 ns.
50
mA
Operating current
I
CC4
t
CK
t
CK(MIN.)
, Io = 0 mA,
CL = 2
-C10
150
170
200
mA
2
(Burst mode)
All bank activated
-C12
125
140
165
CL = 2.5
-C10
190
210
250
-C12
150
170
200
CBR (auto) refresh current
I
CC5
t
RC
t
RC(MIN.)
290
mA
3
Self refresh current
I
CC6
CKE
0.2 V
2
mA
Notes 1.
I
CC1
depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, I
CC1
is measured condition that addresses are changed only one time during t
CK(MIN.)
.
2.
I
CC4
depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, I
CC4
is measured condition that addresses are changed only one time during t
CK(MIN.)
.
3.
I
CC5
is measured on condition that addresses are changed only one time during t
CK(MIN.)
.
13.5 DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Test condition
MIN.
MAX.
Unit Notes
Input leakage current
I
I(L)
V
I
= 0 to 3.6 V, all other pins not under test = 0 V
5
5
μ
A
Output leakage current
I
O(L)
D
OUT
is disabled, V
O
= 0 to V
CC
Q + 0.3 V
5
5
μ
A
High level output voltage
V
OH
I
O
=
12 mA
V
TT
+ 0.6
V
Low level output voltage
V
OL
I
O
= 12 mA
V
TT
0.6
V
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