參數(shù)資料
型號(hào): μPD45D128442
廠商: NEC Corp.
英文描述: 128 M-bit Synchronous DRAM with Double Data Rate(128 同步動(dòng)態(tài)RAM)
中文描述: 128 M位同步雙數(shù)據(jù)速率(128同步動(dòng)態(tài)RAM的內(nèi)存)
文件頁(yè)數(shù): 36/80頁(yè)
文件大?。?/td> 637K
代理商: ΜPD45D128442
36
μ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
12.3 Precharge Termination in Write Cycle
During a burst write cycle without auto precharge, the burst write operation is terminated by a precharge command of
the same banks. In order to write the last input data to the memory cell correctly, t
DPL (MIN.)
must be satisfied. When
the precharge command is issued at the rising edge of the clock (CLK), the invalid data from the burst write cycle
must be masked DM.
CLK
Burst length = 8
Write
DQS
Command
/CAS latency = 2, 2.5
/CLK
CKE
t
DPL
= 1 cycle
PRE
DQ
D1
D2
DM
T0
T2
T1
T3
T4
T5
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