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參數(shù)資料
| 型號： | μPD45D128442 |
| 廠商： | NEC Corp. |
| 英文描述： | 128 M-bit Synchronous DRAM with Double Data Rate(128 同步動態(tài)RAM) |
| 中文描述： | 128 M位同步雙數(shù)據(jù)速率（128同步動態(tài)RAM的內(nèi)存） |
| 文件頁數(shù)： | 13/80頁 |
| 文件大?。?/td> | 637K |
| 代理商： | ΜPD45D128442 |
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13
μ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
CBR (auto) refresh command
(/CS, /RAS, /CAS = Low, /WE, CKE = High)
This command is a request to begin the CBR (auto) refresh operation.
The refresh address is generated internally.
Before executing CBR (auto) refresh, all banks must be precharged.
After this cycle, all banks will be in the idle (precharged) state and ready for a
bank activate command.
During t
RC
(refresh command to refresh or activate command period), the
μ
PD45D128xxx cannot accept any other command.
Fig.7 CBR (auto) refresh
command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0, BA1
Self refresh entry command
(/CS, /RAS, /CAS, CKE = Low, /WE = High)
After the command execution, self refresh operation continues while CKE
remains low.
When CKE goes high, the
μ
PD45D128xxx will exit the self refresh mode.
During self refresh mode, refresh interval and refresh operation are performed
internally, so there is no need for external control.
Before executing self refresh, all banks must be precharged.
Fig.8 Self refresh entry command
/WE
/CAS
/RAS
/CS
CKE
CLK
Add
A10
BA0, BA1
Burst stop command
(/CS, /WE = Low, /RAS, /CAS = High)
This command can stop the current read burst operation.
Fig.9 Burst stop command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0, BA1
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