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參數(shù)資料
| 型號： | μPD45D128442 |
| 廠商： | NEC Corp. |
| 英文描述： | 128 M-bit Synchronous DRAM with Double Data Rate(128 同步動態(tài)RAM) |
| 中文描述： | 128 M位同步雙數(shù)據(jù)速率（128同步動態(tài)RAM的內(nèi)存） |
| 文件頁數(shù)： | 12/80頁 |
| 文件大?。?/td> | 637K |
| 代理商： | ΜPD45D128442 |
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12
μ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
Precharge command
(/CS, /RAS, /WE= Low, /CAS = High)
This command begins precharge operation of the bank selected by BA0, BA1 and
A10. When A10 is High, all banks are precharged, regardless of BA0 and BA1.
When A10 is Low, only the bank selected by BA0 and BA1 is precharged.
After this command, the
μ
PD45D128xxx can't accept the activate command to
the precharging bank during t
RP
(precharge to activate command period).
This command can terminate the current burst operation.
This command corresponds to a conventional DRAM's /RAS rising.
Fig.4 Precharge command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
(Precharge select)
A10
BA0, BA1
Read command
(/CS, /CAS = Low, /RAS, /WE = High)
This command begins the burst read operation. The bank and the burst start
column address are selected by BA0 and BA1 and by A0 through A11
respectively.
Read data is available after /CAS latency requirements which have been met.
And it is synchronized with DQS.
Fig.5 Read command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
(Auto precharge select)
Col.
BA0, BA1
Write command
(/CS, /CAS, /WE = Low, /RAS = High)
This command begins burst write operation. The bank and the burst start column
address are selected by BA0 and BA1 and by A0 through A11 respectively.
Write data must be input by DQ0 through DQ15. Byte mask data must be input
by DM, LDM, and UDM. Both data must be synchronized with DQS that is inputted
after this command.
Fig.6 Write command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
(Auto precharge select)
Col.
BA0, BA1
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