參數(shù)資料
型號(hào)： μPD4564441
廠商： NEC Corp.
英文描述： 64M-bit Synchronous DRAM(64M同步動(dòng)態(tài)RAM)
中文描述： 6400位同步DRAM（6400同步動(dòng)態(tài)RAM）的
文件頁(yè)數(shù)： 8/84頁(yè)
文件大?。?/td> 697K
代理商： ΜPD4564441
8
μ
PD4564441, 4564841, 4564163 for Rev. E
CONTENTS
1.
Input / Output Pin Function ............................................................................................................ 10
2.
Commands ....................................................................................................................................... 11
3.
Simplified State Diagram ................................................................................................................. 14
4.
Truth Table ....................................................................................................................................... 15
4.1
Command Truth Table............................................................................................................................. 15
4.2
DQM Truth Table...................................................................................................................................... 15
4.3
CKE Truth Table....................................................................................................................................... 15
4.4
Operative Command Table ..................................................................................................................... 16
4.5
Command Truth Table for CKE .............................................................................................................. 19
5.
Initialization ...................................................................................................................................... 20
6.
Programming the Mode Register ................................................................................................... 21
7.
Mode Register .................................................................................................................................. 22
7.1
Burst Length and Sequence .................................................................................................................. 23
8.
Address Bits of Bank-Select and Precharge ................................................................................. 24
9.
Precharge ......................................................................................................................................... 25
10. Auto Precharge ................................................................................................................................ 26
10.1
Read with Auto Precharge ................................................................................................................... 26
10.2
Write with Auto Precharge .................................................................................................................. 27
11. Read / Write Command Interval ..................................................................................................... 28
11.1
Read to Read Command Interval ........................................................................................................ 28
11.2
Write to Write Command Interval ........................................................................................................ 28
11.3
Write to Read Command Interval ........................................................................................................ 29
11.4
Read to Write Command Interval ........................................................................................................ 30
12. Burst Termination ............................................................................................................................ 31
12.1
Burst Stop Command .......................................................................................................................... 31
12.2
Precharge Termination ........................................................................................................................ 32
12.2.1
12.2.2
Precharge Termination in READ Cycle .................................................................................... 32
Precharge Termination in WRITE Cycle .................................................................................. 33
相關(guān)PDF資料
PDF描述
μPD4564841 64M-bit Synchronous DRAM(64M同步動(dòng)態(tài)RAM)
μPD4564323 64M-bit Synchronous DRAM(64M 同步動(dòng)態(tài)RAM)
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